Regarding Digital NCO design

Thanks. The multiplied form is just (I*Q). This is sent to a loop
filter(Low pass filter) to get the phase error? But i cant decide the
design idea of this filter. What is the relation between the loop filter's
output and phase increment value when the frequency is locked? Since the
output of loop filter is binary, does it imply a phase error between the
input received signal and reference signal? I am using an averaging filter
as loop filter but can't decide the phase increment value from the filter's
output.


Nusrat




>nowsheen wrote:
>> The loop filter output is the multiplied form of data coming from I and
Q
>> arm of Costas loop. So, after multiplying these two data i am getting
the
>> input of loop filter. How can i know when the phase is dead on? Which
value
>> is this subtracted from? How does the loop filter's output decide
phase
>> increment value?When is the phase locked?
>
>By "multiplied form of data coming from I and Q" do you mean 
>sqrt(I^2+Q^2)? The phase increment is right when the frequency is 
>locked. Then the phase remains steady. When the phase is locked, the 
>phase comparator output is zero.
>
>Jerry
>-- 
>Engineering is the art of making what you want from things you can get.
>�����������������������������������������������������������������������
>

nowsheen wrote:
> Thanks. The multiplied form is just (I*Q). This is sent to a loop
> filter(Low pass filter) to get the phase error? But i cant decide the
> design idea of this filter. What is the relation between the loop filter's
> output and phase increment value when the frequency is locked? Since the
> output of loop filter is binary, does it imply a phase error between the
> input received signal and reference signal? I am using an averaging filter
> as loop filter but can't decide the phase increment value from the filter's
> output.

What is the significance of the product I*Q? In those circumstances 
where I represents cos(x) and Q, sin(x), the product is .5*sin(2*x). Is 
that what you want?

Jerry
-- 
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

On 10/7/2009 4:59 PM, Jerry Avins wrote:
> nowsheen wrote:
>> Thanks. The multiplied form is just (I*Q). This is sent to a loop
>> filter(Low pass filter) to get the phase error? But i cant decide the
>> design idea of this filter. What is the relation between the loop
>> filter's
>> output and phase increment value when the frequency is locked? Since the
>> output of loop filter is binary, does it imply a phase error between the
>> input received signal and reference signal? I am using an averaging
>> filter
>> as loop filter but can't decide the phase increment value from the
>> filter's
>> output.
>
> What is the significance of the product I*Q? In those circumstances
> where I represents cos(x) and Q, sin(x), the product is .5*sin(2*x). Is
> that what you want?
>
> Jerry

For a BPSK signal I*Q is a passable phase detector.   Plot I*Q as a 
phasor rotates through 2pi radians and it makes a usable phase detector 
that locks the constellation to the coordinate axes (where the product 
is zero).

For the OP, start by studying analog Phase-Locked Loops, then study the 
transformation of the analog PLL to a digital form via a 
z-transformation.   This process is described in several books and 
papers from about thirty years ago (e.g., Gardner's PLL book).  One has 
to carefully keep track of the dimensional units for the loop, including 
the phase detector and NCO gains, and that may require some creativity.

Once that is done it becomes fairly straightforward to connect the 
system together digitally.  There are numerous pitfalls along the way if 
you're not careful, though.

-- 
Eric Jacobsen
Minister of Algorithms
Abineau Communications
http://www.abineau.com

Eric Jacobsen wrote:
> On 10/7/2009 4:59 PM, Jerry Avins wrote:
>> nowsheen wrote:
>>> Thanks. The multiplied form is just (I*Q). This is sent to a loop
>>> filter(Low pass filter) to get the phase error? But i cant decide the
>>> design idea of this filter. What is the relation between the loop
>>> filter's
>>> output and phase increment value when the frequency is locked? Since the
>>> output of loop filter is binary, does it imply a phase error between the
>>> input received signal and reference signal? I am using an averaging
>>> filter
>>> as loop filter but can't decide the phase increment value from the
>>> filter's
>>> output.
>>
>> What is the significance of the product I*Q? In those circumstances
>> where I represents cos(x) and Q, sin(x), the product is .5*sin(2*x). Is
>> that what you want?
>>
>> Jerry
> 
> For a BPSK signal I*Q is a passable phase detector.   Plot I*Q as a 
> phasor rotates through 2pi radians and it makes a usable phase detector 
> that locks the constellation to the coordinate axes (where the product 
> is zero).

For many PLLs, the second harmonic is a good choice provided there's a 
way to resolve the phase ambiguity. squaring works, but creates a DC 
level. I*Q doesn't. I was just curious to know the OP's reason for 
choosing it.

> For the OP, start by studying analog Phase-Locked Loops, then study the 
> transformation of the analog PLL to a digital form via a 
> z-transformation.   This process is described in several books and 
> papers from about thirty years ago (e.g., Gardner's PLL book).  One has 
> to carefully keep track of the dimensional units for the loop, including 
> the phase detector and NCO gains, and that may require some creativity.
> 
> Once that is done it becomes fairly straightforward to connect the 
> system together digitally.  There are numerous pitfalls along the way if 
> you're not careful, though.

Jerry
-- 
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

I'm not sure what your phase detector is doing, but I assume the two
states indicate if the phase is leading or lagging with no indication
that the phase is actually aligned.  That means you need to integrate
this signal.  You can use it to increment/decrement a counter and use
the counter output as the phase step in your NCO.  This will be slow
to lock in and you will need to analyze your entire loop for
stability.  Adding the counter as an integrator makes the loop a bit
more complex to analyze.  But the integrating counter will allow the
loop to settle in a state where the error output is equally in both
states indicating an average phase error of zero.  It sounds like your
phase detector is analog, no?  If so, be sure to isolate all digital
noise from the analog phase detector or you will have problems with it
settling and stability.

Rick


On Oct 7, 7:51&#4294967295;pm, "nowsheen" <Nusrat.Nowsh...@student.adfa.edu.au>
wrote:
> Thanks. The multiplied form is just (I*Q). This is sent to a loop
> filter(Low pass filter) to get the phase error? But i cant decide the
> design idea of this filter. What is the relation between the loop filter's
> output and phase increment value when the frequency is locked? Since the
> output of loop filter is binary, does it imply a phase error between the
> input received signal and reference signal? I am using an averaging filter
> as loop filter but can't decide the phase increment value from the filter's
> output.
>
> Nusrat
>
>
>
> >nowsheen wrote:
> >> The loop filter output is the multiplied form of data coming from I and
> Q
> >> arm of Costas loop. So, after multiplying these two data i am getting
> the
> >> input of loop filter. How can i know when the phase is dead on? Which
> value
> >> is this subtracted from? How does the loop filter's output decide
> phase
> >> increment value?When is the phase locked?
>
> >By "multiplied form of data coming from I and Q" do you mean
> >sqrt(I^2+Q^2)? The phase increment is right when the frequency is
> >locked. Then the phase remains steady. When the phase is locked, the
> >phase comparator output is zero.
>
> >Jerry
> >--
> >Engineering is the art of making what you want from things you can get.
> >
>
>

On Oct 10, 5:35=A0am, rickman <gnu...@gmail.com> wrote:
> I'm not sure what your phase detector is doing, but I assume the two
> states indicate if the phase is leading or lagging with no indication
> that the phase is actually aligned. =A0That means you need to integrate
> this signal. =A0You can use it to increment/decrement a counter and use
> the counter output as the phase step in your NCO. =A0This will be slow
> to lock in and you will need to analyze your entire loop for
> stability. =A0Adding the counter as an integrator makes the loop a bit
> more complex to analyze. =A0But the integrating counter will allow the
> loop to settle in a state where the error output is equally in both
> states indicating an average phase error of zero. =A0It sounds like your
> phase detector is analog, no? =A0If so, be sure to isolate all digital
> noise from the analog phase detector or you will have problems with it
> settling and stability.
>
> Rick
>
> On Oct 7, 7:51=A0pm, "nowsheen" <Nusrat.Nowsh...@student.adfa.edu.au>
> wrote:
>
> > Thanks. The multiplied form is just (I*Q). This is sent to a loop
> > filter(Low pass filter) to get the phase error? But i cant decide the
> > design idea of this filter. What is the relation between the loop filte=
r's
> > output and phase increment value when the frequency is locked? Since th=
e
> > output of loop filter is binary, does it imply a phase error between th=
e
> > input received signal and reference signal? I am using an averaging fil=
ter
> > as loop filter but can't decide the phase increment value from the filt=
er's
> > output.
>
> > Nusrat
>
> > >nowsheen wrote:
> > >> The loop filter output is the multiplied form of data coming from I =
and
> > Q
> > >> arm of Costas loop. So, after multiplying these two data i am gettin=
g
> > the
> > >> input of loop filter. How can i know when the phase is dead on? Whic=
h
> > value
> > >> is this subtracted from? How does the loop filter's output decide
> > phase
> > >> increment value?When is the phase locked?
>
> > >By "multiplied form of data coming from I and Q" do you mean
> > >sqrt(I^2+Q^2)? The phase increment is right when the frequency is
> > >locked. Then the phase remains steady. When the phase is locked, the
> > >phase comparator output is zero.
>
> > >Jerry
> > >--
> > >Engineering is the art of making what you want from things you can get=
.

I am designing the costas loop with every component as digital. Input
signal is BPSK modulated data which is multiplied by local carrier
used to modulate the signal.
I have multiplied the digital samples of incoming signal and local
carrier to get I data and the digital sample with 90 degree shifted
local carrier to get Q data. now what can be my next step?I have
designed a Low pass filter to discard twice the frequency component
from data. But after low passing both I and Q data what can be my next
step? How can i decide the input of NCO? Can anyone give me an example
or detailed steps to do this? I have found costas loop designs where I
is multiplied with Q. What is the benefit of this multiplication? How
does it generate phase increment value of NCO?

Thanks
Nowsheen

On Oct 10, 5:35=A0am, rickman <gnu...@gmail.com> wrote:
> I'm not sure what your phase detector is doing, but I assume the two
> states indicate if the phase is leading or lagging with no indication
> that the phase is actually aligned. =A0That means you need to integrate
> this signal. =A0You can use it to increment/decrement a counter and use
> the counter output as the phase step in your NCO. =A0This will be slow
> to lock in and you will need to analyze your entire loop for
> stability. =A0Adding the counter as an integrator makes the loop a bit
> more complex to analyze. =A0But the integrating counter will allow the
> loop to settle in a state where the error output is equally in both
> states indicating an average phase error of zero. =A0It sounds like your
> phase detector is analog, no? =A0If so, be sure to isolate all digital
> noise from the analog phase detector or you will have problems with it
> settling and stability.
>
> Rick
>
> On Oct 7, 7:51=A0pm, "nowsheen" <Nusrat.Nowsh...@student.adfa.edu.au>
> wrote:
>
> > Thanks. The multiplied form is just (I*Q). This is sent to a loop
> > filter(Low pass filter) to get the phase error? But i cant decide the
> > design idea of this filter. What is the relation between the loop filte=
r's
> > output and phase increment value when the frequency is locked? Since th=
e
> > output of loop filter is binary, does it imply a phase error between th=
e
> > input received signal and reference signal? I am using an averaging fil=
ter
> > as loop filter but can't decide the phase increment value from the filt=
er's
> > output.
>
> > Nusrat
>
> > >nowsheen wrote:
> > >> The loop filter output is the multiplied form of data coming from I =
and
> > Q
> > >> arm of Costas loop. So, after multiplying these two data i am gettin=
g
> > the
> > >> input of loop filter. How can i know when the phase is dead on? Whic=
h
> > value
> > >> is this subtracted from? How does the loop filter's output decide
> > phase
> > >> increment value?When is the phase locked?
>
> > >By "multiplied form of data coming from I and Q" do you mean
> > >sqrt(I^2+Q^2)? The phase increment is right when the frequency is
> > >locked. Then the phase remains steady. When the phase is locked, the
> > >phase comparator output is zero.
>
> > >Jerry
> > >--
> > >Engineering is the art of making what you want from things you can get=
.

How can i decide whether the counter is incremented or not and if
incremented by which value?
Thanks
Nusrat

On Oct 7, 8:41=A0pm, Eric Jacobsen <eric.jacob...@ieee.org> wrote:
> On 10/7/2009 4:59 PM, Jerry Avins wrote:
>
>
>
> > nowsheen wrote:
> >> Thanks. The multiplied form is just (I*Q). This is sent to a loop
> >> filter(Low pass filter) to get the phase error? But i cant decide the
> >> design idea of this filter. What is the relation between the loop
> >> filter's
> >> output and phase increment value when the frequency is locked? Since t=
he
> >> output of loop filter is binary, does it imply a phase error between t=
he
> >> input received signal and reference signal? I am using an averaging
> >> filter
> >> as loop filter but can't decide the phase increment value from the
> >> filter's
> >> output.
>
> > What is the significance of the product I*Q? In those circumstances
> > where I represents cos(x) and Q, sin(x), the product is .5*sin(2*x). Is
> > that what you want?
>
> > Jerry
>
> For a BPSK signal I*Q is a passable phase detector. =A0 Plot I*Q as a
> phasor rotates through 2pi radians and it makes a usable phase detector
> that locks the constellation to the coordinate axes (where the product
> is zero).
>
> For the OP, start by studying analog Phase-Locked Loops, then study the
> transformation of the analog PLL to a digital form via a
> z-transformation. =A0 This process is described in several books and
> papers from about thirty years ago (e.g., Gardner's PLL book). =A0One has
> to carefully keep track of the dimensional units for the loop, including
> the phase detector and NCO gains, and that may require some creativity.
>
> Once that is done it becomes fairly straightforward to connect the
> system together digitally. =A0There are numerous pitfalls along the way i=
f
> you're not careful, though.

I*Q will rotate twice as fast as either one, so the zero intercept
with a positive slope occurs at both 0 and 1 pi.  How do you keep the
PLL from locking in at phase 1 pi rather than 0 pi?  What am I
missing?

Rick

On 10/16/2009 4:46 PM, rickman wrote:
> On Oct 7, 8:41 pm, Eric Jacobsen<eric.jacob...@ieee.org>  wrote:
>> On 10/7/2009 4:59 PM, Jerry Avins wrote:
>>
>>
>>
>>> nowsheen wrote:
>>>> Thanks. The multiplied form is just (I*Q). This is sent to a loop
>>>> filter(Low pass filter) to get the phase error? But i cant decide the
>>>> design idea of this filter. What is the relation between the loop
>>>> filter's
>>>> output and phase increment value when the frequency is locked? Since the
>>>> output of loop filter is binary, does it imply a phase error between the
>>>> input received signal and reference signal? I am using an averaging
>>>> filter
>>>> as loop filter but can't decide the phase increment value from the
>>>> filter's
>>>> output.
>>> What is the significance of the product I*Q? In those circumstances
>>> where I represents cos(x) and Q, sin(x), the product is .5*sin(2*x). Is
>>> that what you want?
>>> Jerry
>> For a BPSK signal I*Q is a passable phase detector.   Plot I*Q as a
>> phasor rotates through 2pi radians and it makes a usable phase detector
>> that locks the constellation to the coordinate axes (where the product
>> is zero).
>>
>> For the OP, start by studying analog Phase-Locked Loops, then study the
>> transformation of the analog PLL to a digital form via a
>> z-transformation.   This process is described in several books and
>> papers from about thirty years ago (e.g., Gardner's PLL book).  One has
>> to carefully keep track of the dimensional units for the loop, including
>> the phase detector and NCO gains, and that may require some creativity.
>>
>> Once that is done it becomes fairly straightforward to connect the
>> system together digitally.  There are numerous pitfalls along the way if
>> you're not careful, though.
>
> I*Q will rotate twice as fast as either one, so the zero intercept
> with a positive slope occurs at both 0 and 1 pi.  How do you keep the
> PLL from locking in at phase 1 pi rather than 0 pi?  What am I
> missing?
>
> Rick

Since BPSK is bi-phase, either valid symbol will properly lock on the axis.


-- 
Eric Jacobsen
Minister of Algorithms
Abineau Communications
http://www.abineau.com

hello all , 
 I am having similar problem as Nusrat. Unable to linkup phase detector
output with NCO for loop lock condition. 
Instead of multiplying two signals ( I and Q ) i used atan function to get
phase difference.  Upto this point everything seems working good. But i am
unable to get this signal to drive NCO . Can anybody tell me how this
signal can be used to drive NCO. can anybody provide some code on this part
. 

Any help is appreciable. 

With regards
Pasa

>On 10/16/2009 4:46 PM, rickman wrote:
>> On Oct 7, 8:41 pm, Eric Jacobsen<eric.jacob...@ieee.org>  wrote:
>>> On 10/7/2009 4:59 PM, Jerry Avins wrote:
>>>
>>>
>>>
>>>> nowsheen wrote:
>>>>> Thanks. The multiplied form is just (I*Q). This is sent to a loop
>>>>> filter(Low pass filter) to get the phase error? But i cant decide
the
>>>>> design idea of this filter. What is the relation between the loop
>>>>> filter's
>>>>> output and phase increment value when the frequency is locked? Since
the
>>>>> output of loop filter is binary, does it imply a phase error between
the
>>>>> input received signal and reference signal? I am using an averaging
>>>>> filter
>>>>> as loop filter but can't decide the phase increment value from the
>>>>> filter's
>>>>> output.
>>>> What is the significance of the product I*Q? In those circumstances
>>>> where I represents cos(x) and Q, sin(x), the product is .5*sin(2*x).
Is
>>>> that what you want?
>>>> Jerry
>>> For a BPSK signal I*Q is a passable phase detector.   Plot I*Q as a
>>> phasor rotates through 2pi radians and it makes a usable phase
detector
>>> that locks the constellation to the coordinate axes (where the
product
>>> is zero).
>>>
>>> For the OP, start by studying analog Phase-Locked Loops, then study
the
>>> transformation of the analog PLL to a digital form via a
>>> z-transformation.   This process is described in several books and
>>> papers from about thirty years ago (e.g., Gardner's PLL book).  One
has
>>> to carefully keep track of the dimensional units for the loop,
including
>>> the phase detector and NCO gains, and that may require some
creativity.
>>>
>>> Once that is done it becomes fairly straightforward to connect the
>>> system together digitally.  There are numerous pitfalls along the way
if
>>> you're not careful, though.
>>
>> I*Q will rotate twice as fast as either one, so the zero intercept
>> with a positive slope occurs at both 0 and 1 pi.  How do you keep the
>> PLL from locking in at phase 1 pi rather than 0 pi?  What am I
>> missing?
>>
>> Rick
>
>Since BPSK is bi-phase, either valid symbol will properly lock on the
axis.
>
>
>-- 
>Eric Jacobsen
>Minister of Algorithms
>Abineau Communications
>http://www.abineau.com
>