On Mon, 26 Oct 2009 14:41:38 -0400, Jerry Avins wrote:> Tim Wescott wrote: >> On Mon, 26 Oct 2009 12:27:56 -0400, Jerry Avins wrote: >> >>> Tim Wescott wrote: >>> >>> ... >>> >>>> You can't on a 16-bit machine, but if you're working in an FPGA or >>>> custom logic a 17-bit type is no problem. >>> What do you suppose the OP's context is? >>> >> Homework, but I'm trying not to be ruled by assumptions. > > You're a better man than I am! > > JerryI didn't say I was _succeeding_! -- www.wescottdesign.com
Fixed point arithmetic
Started by ●October 26, 2009
Reply by ●October 26, 20092009-10-26
Reply by ●October 27, 20092009-10-27
On 26 Oct, 16:25, Randy Yates <ya...@ieee.org> wrote:> thunder <ja...@hotmail.com> writes: > > Hi > > > I have a question regarding Fixed point Arithmetic addition. > > > For example, i have two fixed point numbers: > > > a =3D unsigned Q7.8 format (7-bit integer, 8 bit factional). > > b =3D unsigned Q7.8 format ( =A0 =A0" =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ==A0 =A0 " =A0 =A0 =A0 =A0 =A0 =A0).> > > Now a + b =3D c, where c is an unsigned Q8.8 result. > > > Qs: How do I transform c into d, where d is a unsigned Q7.9 result ?? > > There is no way in general to do this conversion and avoid some kind of > nonlinear effect since the range of Q7.9 is smaller than Q8.8. =A0The mos=t> obvious method would be to saturate the Q8.8 result to Q7.9. > > It would be good to know the reason why you're trying to rescale in this > manner - there may be a better way to do things from a higher level > point-of-view. > -- > Randy Yates =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0% "The dreamer, th=e unwoken fool -> Digital Signal Labs =A0 =A0 =A0 =A0 =A0 =A0 =A0% =A0in dreams, no pain wi=ll kiss the brow..."> mailto://ya...@ieee.org =A0 =A0 =A0 =A0 =A0% =A0http://www.digitalsignall=abs.com% 'Eldorado Overture', *Eldorado*, ELO Hello Thanks for all your answers. This is not a homeowrk question, but some actual compute engine that i am trying to design. It turns out that there was a misunderstanding between what i thought the C-model for this compute engine was modeling and the actual implementation in the C-model. My initial understanding was that the C-model was adding two signed Q7.8 numbers (result being a signed Q8.8 number) and then somehow quantising it to signed Q7.9 value. After having posted the question to the newsgroup, the soultions i had mentioned in my post did not seem to be instinctively correct. Thus my next approach was to turn the signed Q8.8 into a saturated Q7.8 value and then add a '0' to the LSB to make it into a signed Q7.9 value. As it turns out, after discussion with the s/w person buliding the C- model, they are not doing the signed Q8.8 to signed Q7.9 transformation. The C-model is adding two signed Q7.9 values to generate a signed Q8.9 value and then adding a third signed Q7.9 value to get a final result of signed Q9.9 value. Thankfully thus i don't have to worry about the transformation. Thanks all once again for all your helpful answers. J
Reply by ●October 27, 20092009-10-27
>On Mon, 26 Oct 2009 10:53:23 -0400, Jerry Avins wrote: > >> thunder wrote: >>> Hi >>> >>> I have a question regarding Fixed point Arithmetic addition. >>> >>> For example, i have two fixed point numbers: >>> >>> a = unsigned Q7.8 format (7-bit integer, 8 bit factional). b =unsigned>>> Q7.8 format ( " " ). >>> >>> Now a + b = c, where c is an unsigned Q8.8 result. >> >> Then there is overflow, just as two Q15.0 integers and getting a Q16.0 >> sum. (Remember the sign bit.) >> >>> Qs: How do I transform c into d, where d is a unsigned Q7.9 result ?? >> >> You can't. Count the bits. (Remember the sign bit.) >> >You can't on a 16-bit machine, but if you're working in an FPGA or custom>logic a 17-bit type is no problem.True, but he specifically said Q7.9, and 7 + 9 was 16 the last time I checked. :-)> >> ... >> >>> QS; Can anyone recommend a good book on Fixed Point and Floatingpoint>>> arithmetic ? >> >> http://www.digitalsignallabs.com/fp.pdf >> >> JerrySteve
