I want to implement soft decision viterbi decoder in FPGA. I have already
implemented hard-decision decoding and the design works fine in xilinx
FPGA. We have implemented "high bit clear circuit" for path metrics
normalization to reduce the area.
Now, i want to implement soft-decision decoding an I need to change the
BMU and ACS modules in my code.
One thing that worries me is the normalization technique that can be used
for soft-decision viterbi. since the calculation of euclidean distance will
result in negative numbers many times, i can't use "high bit clear circuit"
that i have used for hard-decision. So what normalization technique or
methodology, I can use for implementing ACS block in soft-decision