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Oversampling in an ADC to improve performance

Started by Jorge Rivas January 6, 2010
On 1/9/2010 10:25 PM, rickman wrote:
> On Jan 6, 1:49 pm, Jorge Rivas <j.rivas.prietoER...@THIStue.nl> wrote: >> On 1/6/2010 6:51 PM, ralphmalph wrote: >> >> >> >>> On Jan 6, 12:33 pm, Jorge Rivas <j.rivas.prietoER...@THIStue.nl> >>> wrote: >>>> Hi all, >> >>>> I have a communications system that is streaming analog data. On the >>>> receiver side, this data is converted by an ADC with an oversampling of >>>> 4 related to the conversion rate of the DAC on the transmitter. As it is >>>> a system under testing (with variable speed), we don't have a proper >>>> steep analog filter before the ADC, so the oversampling will help to >>>> achieve a better performance. In my receiver (a custom FPGA board), the >>>> ADC gives 4 different streams (synchronized) with the interpolated data. >> >>>> The problem with this interpolated data is that the symbol rate >>>> increases, so there is too many samples for the rest of the receiver. I >>>> know I could discard 3 of the 4 streams and I would have the sent data >>>> rate (fixing so many other troubles :D), but then the oversampling made >>>> would be useless. >> >>>> Another option would be to downsample the samples directly inside the >>>> FPGA, but this would give the same result as in the previous paragraph. >>>> Which is the proper way to handle that high number of samples? >> >>>> Thanks in advance :) >> >>> I am not clear about some of your terminology, but I think you are >>> describing a receiver that is oversampling a bandlimited signal. It >>> does not matter what the rate of the DAC is at the transmitter, only >>> the frequency and bandwidth of the signal being sent. >> >>> You don't say what your signal frequency is, but I assume it is >>> baseband at this point. So if you oversample, you can discard samples >>> simply. But that tosses out all the advantage of oversampling in the >>> first place. To retain the advantages, you need to use a digital low >>> pass filter before decimating. In fact, if you use a FIR filter, you >>> can gain some computational efficiency by omitting the calculations of >>> the the discarded samples. >> >>> If your signal is at a frequency higher than your nyquist rate, you >>> need to consider the frequency downconversion that will happen as you >>> decimate. If this does not put your signal at baseband where you need >>> it, then you must use a digital mixer to achieve the final result, >>> either by mixing before the downconversion or before. Mixing after >>> the downconversion allows you to combine the input low pass filter >>> with the down conversion as described above. >> >>> Do I understand what you are trying to do or have I muffed it? >> >>> Rick >> >> Thanks for your reply, Rick. >> >> The transmitted signal is indeed baseband. The spectrum of the signal is >> pretty flat and has a bandwidth of around 300 MHz. The DAC is sampling >> at 600 MSPS. > > Is this a typo? If your signal has a 300 MHz bandwidth, then you must > sample it at a minimum of 600 MSPS to accurately represent it > discretely. I understand that the DAC is creating the signal, but are > you saying that the ADC is sampling at 2400 MSPS??? That is pretty > durn fast!
Yes, not a typo. The DAC is creating the signal at 600 MSPS to meet Nyquist. The ADC is actually a dual ADC. It is working at 600 MHz but it samples data in both edges. You have then 4 streams of 600 MSPS (one for each edge on each ADC).
> > >> I cannot use a digital low pass filter directly on the input streaming, >> because the clock frequency would be too high for my FPGA. There is >> another problem, though. Each one of the streams of interpolated data >> that go into the FPGA are already parallelized and do not correspond >> directly with the sampled data. The ADC gives 8 bits of resolution per >> sample, but on the FPGA I receive 4 streams of 32-bit wide symbols each. > > Ok, if you don't want to filter the ADC data before you decimate it, > you can toss samples without filtering, but you will not gain any > advantage from the higher sample rate. What you say about the data > being "parallelized" and not corresponding to the sampled data makes > no sense to me. The way the data is bundled at the input to the FPGA > is not material except that you must sort it out inside the FPGA so > that you have a sequential data stream. If you are interleaving > multiple ADCs to increase the sample rate, you just have to interleave > the input data to match. That would use a mux. >
With the parallelization I tried to mean (as John described much better than me) than I am receiving all my data in parallel, with a much lower symbol rate on each stream. So, let's say that I am receiving 16 8-bit symbols, at the same time. Sorry for the sloppy description before...
> >> I can understand what happens when a signal is interpolated or >> decimated, but I ran out of ideas quite fast when there are Serial to >> Parallel converters in the middle. The only thing I can think of is bit >> manipulation... Any idea? > > I think you are confusing yourself. Whether the data is serial or > parallel is irrelevant to this exercise. Data is data. The only > concern is that you keep the order of the samples consistent. > > Your initial post seems to accurately describe your situation. You > can decimate without filtering and get nothing from the oversampling > or you can use a digital filter before decimating which effectively > averages the multiple samples to improve the S/N ratio. > > So what exactly are you not clear on?
I was highly confusing myself, you are right. That, together with some problems in basic DSP (...). Now I think I have everything more clear, but still don't know how to handle the 16 8-bit symbols. Problem is that if that data were serial, I would know how to do the filtering. I cannot serialize the data, as that would give me a stream of 2.4 GSPS, too much for the FPGA to handle serially. Imagine I have a bank of 16 filters, each one applied to each of the 16 streams. Does filtering each one of the streams separately have the same effect as filtering the hypothetical serial 2.4 GSPS from the ADC with the same kind of filter? That would be my main problem now. I think that I tried to explain the setup and got messed with all the descriptions, my fault :/ Jorge