# FIR quantization effect ( implementing in fpga)

Started by January 7, 2010
```hi,
I am trying to implement an FIR filter, fixed point one, using labview
and xilinx core generator. while the labview only method gives good result,
the combination dosn't . so, let me explain how i have done computaion,and
sb cld point are they correct?
i create floating point filter,using kaiser window, of order 54,and
55(nh) coefficients. The max,min values are 0.1544 and -0.1733. to represnt
these,
i need minumum of ceil(3.3 *4) = 14 bits,or Word length. i use Q15
represntaion,with WL 16, Fl=15.
the input is sum of two sine waves, with max =0.877,min =-0.877. again, i
use Q15 representaion.no of samples is nx=640;
Now, for wl 16, for each o.p sample, there are nh multiplications( nh/2 if
so, when x(q15) and h(q15 ) are multiplied, product will be [ 2,30], 2=
integer length and 30=fraction length. these are added nh-1 times, so we
need >= 32+log2(nh-1), or 32+6= 38 as o/p Wl.
now, product will have max=0.877*0.1544 =0.1354, and min= -0.877 *
0.1544=-0.1354. [2,30] can represent this. if these added 54 times, sum
will have max= 0.1354*54=7.31, min=-7.31. so, -7 means that we need atleast
5 integer wl bits,and with fraction length at 30 for full precison, o/p
would be [ 8,30].
so, is this ok? the xilinx core is showing [ 15,17] as o/p.
any help?i need solution urgently.
thnks sid

```
```On Jan 7, 12:37&#2013266080;pm, "sed_y" <se...@yahoo.com> wrote:
> hi,
> &#2013266080;I am trying to implement an FIR filter, fixed point one, using labview
> and xilinx core generator. while the labview only method gives good result,
> the combination dosn't . so, let me explain how i have done computaion,and
> sb cld point are they correct?
> &#2013266080;i create floating point filter,using kaiser window, of order 54,and
> 55(nh) coefficients. The max,min values are 0.1544 and -0.1733. to represnt
> these,
> i need minumum of ceil(3.3 *4) = 14 bits,or Word length. i use Q15
> represntaion,with WL 16, Fl=15.
> the input is sum of two sine waves, with max =0.877,min =-0.877. again, i
> use Q15 representaion.no of samples is nx=640;
> Now, for wl 16, for each o.p sample, there are nh multiplications( nh/2 if
> symmetric), nh-1 additions and delays.
> so, when x(q15) and h(q15 ) are multiplied, product will be [ 2,30], 2=
> integer length and 30=fraction length. these are added nh-1 times, so we
> need >= 32+log2(nh-1), or 32+6= 38 as o/p Wl.
> now, product will have max=0.877*0.1544 =0.1354, and min= -0.877 *
> 0.1544=-0.1354. [2,30] can represent this. if these added 54 times, sum
> will have max= 0.1354*54=7.31, min=-7.31. so, -7 means that we need atleast
> 5 integer wl bits,and with fraction length at 30 for full precison, o/p
> would be [ 8,30].
> so, is this ok? the xilinx core is showing [ 15,17] as o/p.
> any help?i need solution urgently.
> thnks sid

It may be that the Xilinx is returning the result of a multiplication
without the truncation implied by your fixed point fractional
representation. that is, it is not truly implementing fractional fixed
point arithmetic but integer.

Chris
=====================
Chris Bore
BORES Signal Processing
www.bores.com
```