Hi there I am going through the data sheet for AD9445. It is configured to be used in the LVDS mode. The output signals are as such: 14 bit data values(D0+,D0-,.........D13+,D13-) OR- and OR+ (out of range bits) DCO- and DCO + (Data Clock Output) What does the term "Data Clock output" mean??? is it the conversion time the ADC took??? If I were using a buffer and collecting the data values how do I treat the OR and DCO bits. Hope someone help me out. regards Lakshmi
IF sampling ADC
Started by ●January 30, 2010
Reply by ●January 30, 20102010-01-30
lakshmi3489 wrote:> Hi there > I am going through the data sheet for AD9445. It is configured to be > used in the LVDS mode. The output signals are as such: > > 14 bit data values(D0+,D0-,.........D13+,D13-) > > OR- and OR+ (out of range bits) > > DCO- and DCO + (Data Clock Output) > > > What does the term "Data Clock output" mean??? is it the conversion > time the ADC took??? > > If I were using a buffer and collecting the data values how do I treat > the OR and DCO bits. > > > Hope someone help me out.Can't you find reference to it on a timing diagram? It's waveform will probably make its use clear. Does the AD9445 have a serial output mode? Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●January 30, 20102010-01-30
On Jan 30, 8:33�pm, "lakshmi3489" <lakshmi.dorav...@gmail.com> wrote:> Hi there > � �I am going through the data sheet for AD9445. It is configured to be > used in the LVDS mode. The output signals are as such: > > �14 bit data values(D0+,D0-,.........D13+,D13-) > > �OR- and OR+ (out of range bits) > > �DCO- and DCO + (Data Clock Output) > > � �What does the term "Data Clock output" mean??? is it the conversion > time the ADC took??? > > � �If I were using a buffer and collecting the data values how do I treat > the OR and DCO bits. > > � Hope someone help me out. > > regards > LakshmiAre you sure you know what you are doing? Your questions are very basic and it looks like you are missing some basic knowledge. The DCO output is the clock signal you need to use to sample the output data from the ADC. In some cases, as this one, you cannot use the ADC input clock as the clock to sample the output data since there is a time skew between them. So the ADC generates the required clock. The OR signals are just an indication of an over-range. I'm not familiar with the AD9445 device but most ADCs implement the required clipping internally so the OR signals are just there to tell you that the signal is too high for the ADC input. Good luck, Moti
Reply by ●January 30, 20102010-01-30
On Sat, 30 Jan 2010 11:18:34 -0800, Moti Litochevski wrote:> On Jan 30, 8:33 pm, "lakshmi3489" <lakshmi.dorav...@gmail.com> wrote: >> Hi there >> I am going through the data sheet for AD9445. It is configured to >> be >> used in the LVDS mode. The output signals are as such: >> >> 14 bit data values(D0+,D0-,.........D13+,D13-) >> >> OR- and OR+ (out of range bits) >> >> DCO- and DCO + (Data Clock Output) >> >> What does the term "Data Clock output" mean??? is it the >> conversion >> time the ADC took??? >> >> If I were using a buffer and collecting the data values how do I >> treat >> the OR and DCO bits. >> >> Hope someone help me out. >> >> regards >> Lakshmi > > Are you sure you know what you are doing? Your questions are very basic > and it looks like you are missing some basic knowledge. > The DCO output is the clock signal you need to use to sample the output > data from the ADC. In some cases, as this one, you cannot use the ADC > input clock as the clock to sample the output data since there is a time > skew between them. So the ADC generates the required clock. The OR > signals are just an indication of an over-range. I'm not familiar with > the AD9445 device but most ADCs implement the required clipping > internally so the OR signals are just there to tell you that the signal > is too high for the ADC input. Good luck,Note that if the device provides a DCO you're in a realm where you have pay attention to constraints on length-matching all of the signal traces, and probably maintaining some semblance of controlled impedance, too. As Mito said -- if you have to ask, it'll be an uphill climb. -- www.wescottdesign.com
Reply by ●February 1, 20102010-02-01
>On Sat, 30 Jan 2010 11:18:34 -0800, Moti Litochevski wrote: > >> On Jan 30, 8:33 pm, "lakshmi3489" <lakshmi.dorav...@gmail.com> wrote: >>> Hi there >>> I am going through the data sheet for AD9445. It is configuredto>>> be >>> used in the LVDS mode. The output signals are as such: >>> >>> 14 bit data values(D0+,D0-,.........D13+,D13-) >>> >>> OR- and OR+ (out of range bits) >>> >>> DCO- and DCO + (Data Clock Output) >>> >>> What does the term "Data Clock output" mean??? is it the >>> conversion >>> time the ADC took??? >>> >>> If I were using a buffer and collecting the data values how do I >>> treat >>> the OR and DCO bits. >>> >>> Hope someone help me out. >>> >>> regards >>> Lakshmi >> >> Are you sure you know what you are doing? Your questions are verybasic>> and it looks like you are missing some basic knowledge. >> The DCO output is the clock signal you need to use to sample theoutput>> data from the ADC. In some cases, as this one, you cannot use the ADC >> input clock as the clock to sample the output data since there is atime>> skew between them. So the ADC generates the required clock. The OR >> signals are just an indication of an over-range. I'm not familiar with >> the AD9445 device but most ADCs implement the required clipping >> internally so the OR signals are just there to tell you that thesignal>> is too high for the ADC input. Good luck, > >Note that if the device provides a DCO you're in a realm where you have >pay attention to constraints on length-matching all of the signal traces,>and probably maintaining some semblance of controlled impedance, too. >hi Thank you for the speedy replies. I grasp the principle behind it better.Yes, I have taken a better look at the timing diagram.So basically since my data specifications says I have a pipeline latency of 13 clock cycles, I need to keep a watch on the DCO(counting the 13 clock cycles with reference to this) to collect the data at the correct time. One more question, since the ADC is configured as an LVDS type. So it is basically sending the data as two complementary signals so as to increase signal fidelity. Now receiving these two signal, how do I get my digitized signal. Do i just pick one of the complementary signals or does something else have to be done?
Reply by ●February 1, 20102010-02-01
On 1/30/2010 10:19 PM, Tim Wescott wrote:> Note that if the device provides a DCO you're in a realm where you have > pay attention to constraints on length-matching all of the signal traces, > and probably maintaining some semblance of controlled impedance, too. >Length-matching, probably not. The ADC is going at 125 MSPS. The signal goes along the wires at 6 inches/ns or so. That's four feet for a single cycle. You'd need some crazy layout for length matching to be a problem. The DCO is to cope with delays in the device, which turn out to be about 3ns or so. Impedance matching, well, maybe. IIRC some AD devices have awful LVDS outputs without termination resistors. Yuk. HTH., Syms.
Reply by ●February 1, 20102010-02-01
On Feb 1, 12:44�pm, "lakshmi3489" <lakshmi.dorav...@gmail.com> wrote:> >On Sat, 30 Jan 2010 11:18:34 -0800, Moti Litochevski wrote: > > >> On Jan 30, 8:33�pm, "lakshmi3489" <lakshmi.dorav...@gmail.com> wrote: > >>> Hi there > >>> � �I am going through the data sheet for AD9445. It is configured > to > >>> � �be > >>> used in the LVDS mode. The output signals are as such: > > >>> �14 bit data values(D0+,D0-,.........D13+,D13-) > > >>> �OR- and OR+ (out of range bits) > > >>> �DCO- and DCO + (Data Clock Output) > > >>> � �What does the term "Data Clock output" mean??? is it the > >>> � �conversion > >>> time the ADC took??? > > >>> � �If I were using a buffer and collecting the data values how do I > >>> � �treat > >>> the OR and DCO bits. > > >>> � Hope someone help me out. > > >>> regards > >>> Lakshmi > > >> Are you sure you know what you are doing? Your questions are very > basic > >> and it looks like you are missing some basic knowledge. > >> The DCO output is the clock signal you need to use to sample the > output > >> data from the ADC. In some cases, as this one, you cannot use the ADC > >> input clock as the clock to sample the output data since there is a > time > >> skew between them. So the ADC generates the required clock. The OR > >> signals are just an indication of an over-range. I'm not familiar with > >> the AD9445 device but most ADCs implement the required clipping > >> internally so the OR signals are just there to tell you that the > signal > >> is too high for the ADC input. Good luck, > > >Note that if the device provides a DCO you're in a realm where you have > >pay attention to constraints on length-matching all of the signal traces, > >and probably maintaining some semblance of controlled impedance, too. > > hi > > �Thank you for the speedy replies. > > � I grasp the principle behind it better.Yes, I have taken a better look > at the timing diagram.So basically since my data specifications says I have > a pipeline latency of 13 clock cycles, I need to keep a watch on the > DCO(counting the 13 clock cycles with reference to this) to collect the > data at the correct time. > > � � One more question, since the ADC is configured as an LVDS type. So it > is basically sending the data as two complementary signals so as to > increase signal fidelity. > > � �Now receiving these two signal, how do I get my digitized signal. Do i > just pick one of the complementary signals or does something else have to > be done?To receive an LVDS signal you need to have an LVDS input buffer. If you are planning to collect the samples in an FPGA then most FPGAs today have the required input buffers. BTW: the ADC latency of 13 clock cycles shouldn't concern you. A new sample is valid at every rising/falling edge of the DCO signal. Moti
Reply by ●February 1, 20102010-02-01
On Mon, 01 Feb 2010 04:44:05 -0600, lakshmi3489 wrote:>>On Sat, 30 Jan 2010 11:18:34 -0800, Moti Litochevski wrote: >> >>> On Jan 30, 8:33 pm, "lakshmi3489" <lakshmi.dorav...@gmail.com> wrote: >>>> Hi there >>>> I am going through the data sheet for AD9445. It is configured > to >>>> be >>>> used in the LVDS mode. The output signals are as such: >>>> >>>> 14 bit data values(D0+,D0-,.........D13+,D13-) >>>> >>>> OR- and OR+ (out of range bits) >>>> >>>> DCO- and DCO + (Data Clock Output) >>>> >>>> What does the term "Data Clock output" mean??? is it the >>>> conversion >>>> time the ADC took??? >>>> >>>> If I were using a buffer and collecting the data values how do I >>>> treat >>>> the OR and DCO bits. >>>> >>>> Hope someone help me out. >>>> >>>> regards >>>> Lakshmi >>> >>> Are you sure you know what you are doing? Your questions are very > basic >>> and it looks like you are missing some basic knowledge. The DCO output >>> is the clock signal you need to use to sample the > output >>> data from the ADC. In some cases, as this one, you cannot use the ADC >>> input clock as the clock to sample the output data since there is a > time >>> skew between them. So the ADC generates the required clock. The OR >>> signals are just an indication of an over-range. I'm not familiar with >>> the AD9445 device but most ADCs implement the required clipping >>> internally so the OR signals are just there to tell you that the > signal >>> is too high for the ADC input. Good luck, >> >>Note that if the device provides a DCO you're in a realm where you have >>pay attention to constraints on length-matching all of the signal >>traces, > >>and probably maintaining some semblance of controlled impedance, too. >> > hi > > Thank you for the speedy replies. > > I grasp the principle behind it better.Yes, I have taken a better look > at the timing diagram.So basically since my data specifications says I > have a pipeline latency of 13 clock cycles, I need to keep a watch on > the DCO(counting the 13 clock cycles with reference to this) to collect > the data at the correct time. > > > One more question, since the ADC is configured as an LVDS type. So > it > is basically sending the data as two complementary signals so as to > increase signal fidelity. > > Now receiving these two signal, how do I get my digitized signal. Do > i > just pick one of the complementary signals or does something else have > to be done?Normally one uses an LVDS converter, to whatever logic family you're using. There are probably ways to cheat it, but it's been long enough since I've done circuit design that don't know any reliable methods. -- www.wescottdesign.com
Reply by ●February 1, 20102010-02-01
On Mon, 01 Feb 2010 10:45:20 +0000, Symon wrote:> On 1/30/2010 10:19 PM, Tim Wescott wrote: >> Note that if the device provides a DCO you're in a realm where you have >> pay attention to constraints on length-matching all of the signal >> traces, and probably maintaining some semblance of controlled >> impedance, too. >> > Length-matching, probably not. The ADC is going at 125 MSPS. The signal > goes along the wires at 6 inches/ns or so. That's four feet for a single > cycle. You'd need some crazy layout for length matching to be a problem. > The DCO is to cope with delays in the device, which turn out to be about > 3ns or so.I should have clarified: by "pay attention" I mean to remember the distance/time relatinship and think how closely the traces need to be matched. If that distance ends up being three times the circumference of the proposed board, then you're safe to make a conscious decision to stop thinking about it. Of course, a 200 foot long board is a rarity... -- www.wescottdesign.com
Reply by ●February 3, 20102010-02-03
>On Feb 1, 12:44=A0pm, "lakshmi3489" <lakshmi.dorav...@gmail.com> wrote: >> >On Sat, 30 Jan 2010 11:18:34 -0800, Moti Litochevski wrote: >> >> >> On Jan 30, 8:33=A0pm, "lakshmi3489" <lakshmi.dorav...@gmail.com>wrote=>: >> >>> Hi there >> >>> =A0 =A0I am going through the data sheet for AD9445. It isconfigured>> to >> >>> =A0 =A0be >> >>> used in the LVDS mode. The output signals are as such: >> >> >>> =A014 bit data values(D0+,D0-,.........D13+,D13-) >> >> >>> =A0OR- and OR+ (out of range bits) >> >> >>> =A0DCO- and DCO + (Data Clock Output) >> >> >>> =A0 =A0What does the term "Data Clock output" mean??? is it the >> >>> =A0 =A0conversion >> >>> time the ADC took??? >> >> >>> =A0 =A0If I were using a buffer and collecting the data values howdo=> I >> >>> =A0 =A0treat >> >>> the OR and DCO bits. >> >> >>> =A0 Hope someone help me out. >> >> >>> regards >> >>> Lakshmi >> >> >> Are you sure you know what you are doing? Your questions are very >> basic >> >> and it looks like you are missing some basic knowledge. >> >> The DCO output is the clock signal you need to use to sample the >> output >> >> data from the ADC. In some cases, as this one, you cannot use theADC>> >> input clock as the clock to sample the output data since there is a >> time >> >> skew between them. So the ADC generates the required clock. The OR >> >> signals are just an indication of an over-range. I'm not familiarwith>> >> the AD9445 device but most ADCs implement the required clipping >> >> internally so the OR signals are just there to tell you that the >> signal >> >> is too high for the ADC input. Good luck, >> >> >Note that if the device provides a DCO you're in a realm where youhave>> >pay attention to constraints on length-matching all of the signaltraces=>, >> >and probably maintaining some semblance of controlled impedance, too. >> >> hi >> >> =A0Thank you for the speedy replies. >> >> =A0 I grasp the principle behind it better.Yes, I have taken a betterloo=>k >> at the timing diagram.So basically since my data specifications says Iha=>ve >> a pipeline latency of 13 clock cycles, I need to keep a watch on the >> DCO(counting the 13 clock cycles with reference to this) to collectthe>> data at the correct time. >> >> =A0 =A0 One more question, since the ADC is configured as an LVDS type.S=>o it >> is basically sending the data as two complementary signals so as to >> increase signal fidelity. >> >> =A0 =A0Now receiving these two signal, how do I get my digitizedsignal. =>Do i >> just pick one of the complementary signals or does something else haveto>> be done? > >To receive an LVDS signal you need to have an LVDS input buffer. >If you are planning to collect the samples in an FPGA then most FPGAs >today have the required input buffers. > >BTW: the ADC latency of 13 clock cycles shouldn't concern you. A new >sample is valid at every rising/falling edge of the DCO signal. > >Moti >great I do have a differential input fifo, so i can get my input this way. I do need a clarification on what was said before though about the latency of the adc not concerning me, i read that though new data is available at every clock cycle ,the data lags the conversion by the pipeline delay plus the output delay. could anyone please clarify on this??
