Hi Group I have a non quadrature signal at 3 MHz. I need to convert it to quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing rate at the next stage. What do you experts think would be the best method in terms of resources (for an fpga) or is there much difference? 1 Hilbert Transformer 2 Multiply by a 1.5 Mhz sine and cosine and then filter to get rid of the 4.5 Mhz sum signal. Alternatively, are there any smart tricks that could do this more efficiently? Many Thanks Bob
Converting non quadrature signal to quadrature
Started by ●March 25, 2010
Reply by ●March 25, 20102010-03-25
Bob wrote:> Hi Group > > I have a non quadrature signal at 3 MHz. I need to convert it to > quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing > rate at the next stage. What do you experts think would be the best > method in terms of resources (for an fpga) or is there much > difference? > > 1 Hilbert Transformer > 2 Multiply by a 1.5 Mhz sine and cosine and then filter to get rid of > the 4.5 Mhz sum signal. > > Alternatively, are there any smart tricks that could do this more > efficiently?Either will work, and it's probably a toss up whether 1 or 2 is best in terms of circuit area and speed requirements (both have been done in analog circuits). But this is a little block in a bigger system, and you're doing something that -- on the face of it -- sounds a bit odd. What are you really trying to do? Normally you want I and Q signals so you can do your processing at baseband. Why don't you demodulate it straight down to DC by multiplying it by 3MHz sine and cosine waves, and filtering as appropriate? -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
Reply by ●March 25, 20102010-03-25
Bob wrote:> Hi Group > > I have a non quadrature signal at 3 MHz. I need to convert it to > quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing > rate at the next stage. What do you experts think would be the best > method in terms of resources (for an fpga) or is there much > difference? > > 1 Hilbert Transformer > 2 Multiply by a 1.5 Mhz sine and cosine and then filter to get rid of > the 4.5 Mhz sum signal. > > Alternatively, are there any smart tricks that could do this more > efficiently?You will have to process the same number of samples either way. 1.5M I plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz bandwidth, you need 3 M samples/sec. They can be all regular samples, half I and half Q, half I and half dI/dt, or any other set. Jerry -- Discovery consists of seeing what everybody has seen, and thinking what nobody has thought. .. Albert Szent-Gyorgi �����������������������������������������������������������������������
Reply by ●March 25, 20102010-03-25
Jerry Avins <jya@ieee.org> wrote:>> I have a non quadrature signal at 3 MHz. I need to convert it to >> quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing >> rate at the next stage. What do you experts think would be the best >> method in terms of resources (for an fpga) or is there much >> difference?(snip)> You will have to process the same number of samples either way. 1.5M I > plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz > bandwidth, you need 3 M samples/sec. They can be all regular samples, > half I and half Q, half I and half dI/dt, or any other set.There might be some cases where quadrature sampling is better, though I am not convinced that there are many. 3MHz isn't fast, so speed probably isn't the reason here. In the case where speed is, you can put two ADCs outside the FPGA and separately clock the two. (Ignoring problems due to non-linearity in the ADCs.) Now, is it better to do the IQ conversion in the analog domain and then send it into the FPGA (More analog circuitry, less FPGA resources) or just sample and ADC at 3MHz, and do the IQ conversion in digital logic? It seems to me that to do it right, you need carefully matched analog filters, where it is easy to do in the digital domain without worry about matching of filters. -- glen
Reply by ●March 25, 20102010-03-25
glen herrmannsfeldt wrote:> Jerry Avins <jya@ieee.org> wrote: > >>> I have a non quadrature signal at 3 MHz. I need to convert it to >>> quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing >>> rate at the next stage. What do you experts think would be the best >>> method in terms of resources (for an fpga) or is there much >>> difference? > (snip) > >> You will have to process the same number of samples either way. 1.5M I >> plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz >> bandwidth, you need 3 M samples/sec. They can be all regular samples, >> half I and half Q, half I and half dI/dt, or any other set. > > There might be some cases where quadrature sampling is better, > though I am not convinced that there are many. > > 3MHz isn't fast, so speed probably isn't the reason here. > > In the case where speed is, you can put two ADCs outside the > FPGA and separately clock the two. (Ignoring problems due to > non-linearity in the ADCs.) > > Now, is it better to do the IQ conversion in the analog domain > and then send it into the FPGA (More analog circuitry, less > FPGA resources) or just sample and ADC at 3MHz, and do the > IQ conversion in digital logic? > > It seems to me that to do it right, you need carefully matched > analog filters, where it is easy to do in the digital domain > without worry about matching of filters. > > -- glenPotayto, potahto. Mathematically it's the same to do it in analog or digital. Practically you have all sorts of channel matching issues if you do it in analog, so if you can get away with it, you'd rather just sample fast and downconvert digitally. 3MHz is very slow these days. I'd go as far as to say that if you _did_ have a carrier that was too fast for all-digital conversion, and unless bandwidth considerations ruled it out, you'd be better off to do a traditional superhet stage to a lower IF, filter, and downconvert to baseband from there. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
Reply by ●March 26, 20102010-03-26
On Mar 25, 4:00=A0pm, Tim Wescott <t...@seemywebsite.now> wrote:> glen herrmannsfeldt wrote: > > Jerry Avins <j...@ieee.org> wrote: > > >>> I have a non quadrature signal at 3 MHz. I need to convert it to > >>> quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing > >>> rate at the next stage. What do you experts think would be the best > >>> method in terms of resources (for an fpga) or is there much > >>> difference? > > (snip) > > >> You will have to process the same number of samples either way. 1.5M I > >> plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz > >> bandwidth, you need 3 M samples/sec. They can be all regular samples, > >> half I and half Q, half I and half dI/dt, or any other set. > > > There might be some cases where quadrature sampling is better, > > though I am not convinced that there are many. =A0 > > > 3MHz isn't fast, so speed probably isn't the reason here. > > > In the case where speed is, you can put two ADCs outside the > > FPGA and separately clock the two. =A0(Ignoring problems due to > > non-linearity in the ADCs.) =A0 > > > Now, is it better to do the IQ conversion in the analog domain > > and then send it into the FPGA =A0(More analog circuitry, less > > FPGA resources) =A0or just sample and ADC at 3MHz, and do the > > IQ conversion in digital logic? > > > It seems to me that to do it right, you need carefully matched > > analog filters, where it is easy to do in the digital domain > > without worry about matching of filters. > > > -- glen > > Potayto, potahto. > > Mathematically it's the same to do it in analog or digital. =A0Practicall=y> you have all sorts of channel matching issues if you do it in analog, so > if you can get away with it, you'd rather just sample fast and > downconvert digitally. > > 3MHz is very slow these days. > > I'd go as far as to say that if you _did_ have a carrier that was too > fast for all-digital conversion, and unless bandwidth considerations > ruled it out, you'd be better off to do a traditional superhet stage to > a lower IF, filter, and downconvert to baseband from there. > > -- > Tim Wescott > Control system and signal processing consultingwww.wescottdesign.com- Hid=e quoted text -> > - Show quoted text -Also if instead of trying to implement a 0 degree and a 90 degree set of filters (with overall delays to ensure causality) you can simply design a pair of filters with +- 45 degrees of phase shift. The filters will have impulse responses that are mirrors of each other, have exactly the same amplitude response and if you make the response symmetrical, then half of the coefs become zero. See here: http://www.claysturner.com/dsp/ASG.pdf I've used this technique in receivers and it works quite well. Clay
Reply by ●March 26, 20102010-03-26
Clay wrote:> On Mar 25, 4:00 pm, Tim Wescott <t...@seemywebsite.now> wrote: > >>glen herrmannsfeldt wrote: >> >>>Jerry Avins <j...@ieee.org> wrote: >> >>>>>I have a non quadrature signal at 3 MHz. I need to convert it to >>>>>quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing >>>>>rate at the next stage. What do you experts think would be the best >>>>>method in terms of resources (for an fpga) or is there much >>>>>difference? >>> >>>(snip) >> >>>>You will have to process the same number of samples either way. 1.5M I >>>>plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz >>>>bandwidth, you need 3 M samples/sec. They can be all regular samples, >>>>half I and half Q, half I and half dI/dt, or any other set. >> >>>There might be some cases where quadrature sampling is better, >>>though I am not convinced that there are many. >> >>>3MHz isn't fast, so speed probably isn't the reason here. >> >>>In the case where speed is, you can put two ADCs outside the >>>FPGA and separately clock the two. (Ignoring problems due to >>>non-linearity in the ADCs.) >> >>>Now, is it better to do the IQ conversion in the analog domain >>>and then send it into the FPGA (More analog circuitry, less >>>FPGA resources) or just sample and ADC at 3MHz, and do the >>>IQ conversion in digital logic? >> >>>It seems to me that to do it right, you need carefully matched >>>analog filters, where it is easy to do in the digital domain >>>without worry about matching of filters. >> >>>-- glen >> >>Potayto, potahto. >> >>Mathematically it's the same to do it in analog or digital. Practically >>you have all sorts of channel matching issues if you do it in analog, so >>if you can get away with it, you'd rather just sample fast and >>downconvert digitally. >> >>3MHz is very slow these days. >> >>I'd go as far as to say that if you _did_ have a carrier that was too >>fast for all-digital conversion, and unless bandwidth considerations >>ruled it out, you'd be better off to do a traditional superhet stage to >>a lower IF, filter, and downconvert to baseband from there. >> >>-- >>Tim Wescott >>Control system and signal processing consultingwww.wescottdesign.com- Hide quoted text - >> >>- Show quoted text - > > > Also if instead of trying to implement a 0 degree and a 90 degree set > of filters (with overall delays to ensure causality) you can simply > design a pair of filters with +- 45 degrees of phase shift. The > filters will have impulse responses that are mirrors of each other, > have exactly the same amplitude response and if you make the response > symmetrical, then half of the coefs become zero. See here: > > http://www.claysturner.com/dsp/ASG.pdf > > I've used this technique in receivers and it works quite well. > > ClayAlso, if the goal is sample rate reduction, the efficient solution could be a 2-band filterbank rather then quadrature. VLV
Reply by ●March 26, 20102010-03-26
On Mar 26, 11:07=A0am, Vladimir Vassilevsky <nos...@nowhere.com> wrote:> Clay wrote: > > On Mar 25, 4:00 pm, Tim Wescott <t...@seemywebsite.now> wrote: > > >>glen herrmannsfeldt wrote: > > >>>Jerry Avins <j...@ieee.org> wrote: > > >>>>>I have a non quadrature signal at 3 MHz. I need to convert it to > >>>>>quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing > >>>>>rate at the next stage. What do you experts think would be the best > >>>>>method in terms of resources (for an fpga) or is there much > >>>>>difference? > > >>>(snip) > > >>>>You will have to process the same number of samples either way. 1.5M =I> >>>>plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz > >>>>bandwidth, you need 3 M samples/sec. They can be all regular samples, > >>>>half I and half Q, half I and half dI/dt, or any other set. > > >>>There might be some cases where quadrature sampling is better, > >>>though I am not convinced that there are many. =A0 > > >>>3MHz isn't fast, so speed probably isn't the reason here. > > >>>In the case where speed is, you can put two ADCs outside the > >>>FPGA and separately clock the two. =A0(Ignoring problems due to > >>>non-linearity in the ADCs.) =A0 > > >>>Now, is it better to do the IQ conversion in the analog domain > >>>and then send it into the FPGA =A0(More analog circuitry, less > >>>FPGA resources) =A0or just sample and ADC at 3MHz, and do the > >>>IQ conversion in digital logic? > > >>>It seems to me that to do it right, you need carefully matched > >>>analog filters, where it is easy to do in the digital domain > >>>without worry about matching of filters. > > >>>-- glen > > >>Potayto, potahto. > > >>Mathematically it's the same to do it in analog or digital. =A0Practica=lly> >>you have all sorts of channel matching issues if you do it in analog, s=o> >>if you can get away with it, you'd rather just sample fast and > >>downconvert digitally. > > >>3MHz is very slow these days. > > >>I'd go as far as to say that if you _did_ have a carrier that was too > >>fast for all-digital conversion, and unless bandwidth considerations > >>ruled it out, you'd be better off to do a traditional superhet stage to > >>a lower IF, filter, and downconvert to baseband from there. > > >>-- > >>Tim Wescott > >>Control system and signal processing consultingwww.wescottdesign.com-Hi=de quoted text -> > >>- Show quoted text - > > > Also if instead of trying to implement a 0 degree and a 90 degree set > > of filters (with overall delays to ensure causality) you can simply > > design a pair of filters with +- 45 degrees of phase shift. The > > filters will have impulse responses that are mirrors of each other, > > have exactly the same amplitude response and if you make the response > > symmetrical, then half of the coefs become zero. See here: > > >http://www.claysturner.com/dsp/ASG.pdf > > > I've used this technique in receivers and it works quite well. > > > Clay > > Also, if the goal is sample rate reduction, the efficient solution could > be a 2-band filterbank rather then quadrature. > > VLV- Hide quoted text - > > - Show quoted text -As Tim alluded to, it all depends on what the OP plans to do with his signal. Clay
Reply by ●March 26, 20102010-03-26
Clay wrote:> On Mar 26, 11:07 am, Vladimir Vassilevsky <nos...@nowhere.com> wrote: >> Clay wrote: >>> On Mar 25, 4:00 pm, Tim Wescott <t...@seemywebsite.now> wrote: >>>> glen herrmannsfeldt wrote: >>>>> Jerry Avins <j...@ieee.org> wrote: >>>>>>> I have a non quadrature signal at 3 MHz. I need to convert it to >>>>>>> quadrature (I and Q) at 1.5 MHz to that I can reduce the sampleing >>>>>>> rate at the next stage. What do you experts think would be the best >>>>>>> method in terms of resources (for an fpga) or is there much >>>>>>> difference? >>>>> (snip) >>>>>> You will have to process the same number of samples either way. 1.5M I >>>>>> plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 MHz >>>>>> bandwidth, you need 3 M samples/sec. They can be all regular samples, >>>>>> half I and half Q, half I and half dI/dt, or any other set. >>>>> There might be some cases where quadrature sampling is better, >>>>> though I am not convinced that there are many. >>>>> 3MHz isn't fast, so speed probably isn't the reason here. >>>>> In the case where speed is, you can put two ADCs outside the >>>>> FPGA and separately clock the two. (Ignoring problems due to >>>>> non-linearity in the ADCs.) >>>>> Now, is it better to do the IQ conversion in the analog domain >>>>> and then send it into the FPGA (More analog circuitry, less >>>>> FPGA resources) or just sample and ADC at 3MHz, and do the >>>>> IQ conversion in digital logic? >>>>> It seems to me that to do it right, you need carefully matched >>>>> analog filters, where it is easy to do in the digital domain >>>>> without worry about matching of filters. >>>>> -- glen >>>> Potayto, potahto. >>>> Mathematically it's the same to do it in analog or digital. Practically >>>> you have all sorts of channel matching issues if you do it in analog, so >>>> if you can get away with it, you'd rather just sample fast and >>>> downconvert digitally. >>>> 3MHz is very slow these days. >>>> I'd go as far as to say that if you _did_ have a carrier that was too >>>> fast for all-digital conversion, and unless bandwidth considerations >>>> ruled it out, you'd be better off to do a traditional superhet stage to >>>> a lower IF, filter, and downconvert to baseband from there. >>>> -- >>>> Tim Wescott >>>> Control system and signal processing consultingwww.wescottdesign.com-Hide quoted text - >>>> - Show quoted text - >>> Also if instead of trying to implement a 0 degree and a 90 degree set >>> of filters (with overall delays to ensure causality) you can simply >>> design a pair of filters with +- 45 degrees of phase shift. The >>> filters will have impulse responses that are mirrors of each other, >>> have exactly the same amplitude response and if you make the response >>> symmetrical, then half of the coefs become zero. See here: >>> http://www.claysturner.com/dsp/ASG.pdf >>> I've used this technique in receivers and it works quite well. >>> Clay >> Also, if the goal is sample rate reduction, the efficient solution could >> be a 2-band filterbank rather then quadrature. >> >> VLV- Hide quoted text - >> >> - Show quoted text - > > As Tim alluded to, it all depends on what the OP plans to do with his > signal.We need to hear from Bob again in order to proceed usefully. Jerry -- Discovery consists of seeing what everybody has seen, and thinking what nobody has thought. .. Albert Szent-Gyorgi �����������������������������������������������������������������������
Reply by ●March 27, 20102010-03-27
On 26 Mar, 15:31, Jerry Avins <j...@ieee.org> wrote:> Clay wrote: > > On Mar 26, 11:07 am, Vladimir Vassilevsky <nos...@nowhere.com> wrote: > >> Clay wrote: > >>> On Mar 25, 4:00 pm, Tim Wescott <t...@seemywebsite.now> wrote: > >>>> glen herrmannsfeldt wrote: > >>>>> Jerry Avins <j...@ieee.org> wrote: > >>>>>>> I have a non quadrature signal at 3 MHz. I need to convert it to > >>>>>>> quadrature (I and Q) at 1.5 MHz to that I can reduce the samplein=g> >>>>>>> rate at the next stage. What do you experts think would be the be=st> >>>>>>> method in terms of resources (for an fpga) or is there much > >>>>>>> difference? > >>>>> (snip) > >>>>>> You will have to process the same number of samples either way. 1.=5M I> >>>>>> plus 1.5M Q is still 3 M samples either way. Whatever, for a 1.i5 =MHz> >>>>>> bandwidth, you need 3 M samples/sec. They can be all regular sampl=es,> >>>>>> half I and half Q, half I and half dI/dt, or any other set. > >>>>> There might be some cases where quadrature sampling is better, > >>>>> though I am not convinced that there are many. =A0 > >>>>> 3MHz isn't fast, so speed probably isn't the reason here. > >>>>> In the case where speed is, you can put two ADCs outside the > >>>>> FPGA and separately clock the two. =A0(Ignoring problems due to > >>>>> non-linearity in the ADCs.) =A0 > >>>>> Now, is it better to do the IQ conversion in the analog domain > >>>>> and then send it into the FPGA =A0(More analog circuitry, less > >>>>> FPGA resources) =A0or just sample and ADC at 3MHz, and do the > >>>>> IQ conversion in digital logic? > >>>>> It seems to me that to do it right, you need carefully matched > >>>>> analog filters, where it is easy to do in the digital domain > >>>>> without worry about matching of filters. > >>>>> -- glen > >>>> Potayto, potahto. > >>>> Mathematically it's the same to do it in analog or digital. =A0Pract=ically> >>>> you have all sorts of channel matching issues if you do it in analog=, so> >>>> if you can get away with it, you'd rather just sample fast and > >>>> downconvert digitally. > >>>> 3MHz is very slow these days. > >>>> I'd go as far as to say that if you _did_ have a carrier that was to=o> >>>> fast for all-digital conversion, and unless bandwidth considerations > >>>> ruled it out, you'd be better off to do a traditional superhet stage=to> >>>> a lower IF, filter, and downconvert to baseband from there. > >>>> -- > >>>> Tim Wescott > >>>> Control system and signal processing consultingwww.wescottdesign.com=-Hidequoted text -> >>>> - Show quoted text - > >>> Also if instead of trying to implement a 0 degree and a 90 degree set > >>> of filters (with overall delays to ensure causality) you can simply > >>> design a pair of filters with +- 45 degrees of phase shift. The > >>> filters will have impulse responses that are mirrors of each other, > >>> have exactly the same amplitude response and if you make the response > >>> symmetrical, then half of the coefs become zero. See here: > >>>http://www.claysturner.com/dsp/ASG.pdf > >>> I've used this technique in receivers and it works quite well. > >>> Clay > >> Also, if the goal is sample rate reduction, the efficient solution cou=ld> >> be a 2-band filterbank rather then quadrature. > > >> VLV- Hide quoted text - > > >> - Show quoted text - > > > As Tim alluded to, it all depends on what the OP plans to do with his > > signal. > > We need to hear from Bob again in order to proceed usefully. > > Jerry > -- > Discovery consists of seeing what everybody has seen, and thinking what > nobody has thought. =A0 =A0.. Albert Szent-Gyorgi > =AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF==AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF= =AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF Hi, Apolgies for not replying and thanking you all for your feedback. I had to take a few days away from work. Anyway, here's what i've got.... The signal at 3 Mhz COFDM data (using a 2048 pt IFFT). The 3 MHz IF is non quadrature. I want to get it into quadrature format to that I can feed it into a FFT. An added benefit of this is that I can also half the sampling rate. All of the signal processing will be done in an FPGA so I was just trying to find out what method would be the most efficient to implement. I've never used a HT in a project before but it would seem more efficient as multiplying by cos and sine method will require a filter on the output of each branch. Any feedback, suggestions is much appreciated. Many Thanks Bob
