DPLL jitter

Hi all.

We are using a DPLL synthesized in an FPGA as a tracking bandpass filter.
The PLL design is based on some older IEEE papers (late 70's) and uses a
binary phase detector and a sequential loop filter (a "Variable Reset
Random Walk Filter" or "VR-RMF" in dsp jargon), essentially we
reimplemented this open cores project :
http://opencores.org/project,dpll_rwf (Boy would it have saved me time to
have known about his core!) 

The paper which this design is based on (reference 3 on that open cores
page) experimentally predicts frequency jitter reduction of ~5-10 fold over
input jitter on a relatively noisy signal. We are getting approximately 2
fold reduction, but even if we got the ideal jitter filtering, it would not
be enough for us. Ideally we want 50-100 fold jitter reduction, but we will
take anything over 2 fold for now.

When we feed the dpll a essentially jitter free signal (~0.5mHz jitter at
700KHz from a very expensive Stanford Research Systems function generator)
or if we let the dpll run as an open loop we find that the dpll has an
intrinsic jitter of approximately 2 mHz at 700KHz with a 100MHz clock. 

My question is, is there anyway to reduce the output jitter of our DPLL,
either through some kind of filtering afterwards in the design or perhaps 
something more substantial when it comes to clock choice or output routing
on the physical board itself. 

On 06/12/2010 09:50 PM, crasic wrote:
> Hi all.
>
> We are using a DPLL synthesized in an FPGA as a tracking bandpass filter.
> The PLL design is based on some older IEEE papers (late 70's) and uses a
> binary phase detector and a sequential loop filter (a "Variable Reset
> Random Walk Filter" or "VR-RMF" in dsp jargon), essentially we
> reimplemented this open cores project :
> http://opencores.org/project,dpll_rwf (Boy would it have saved me time to
> have known about his core!)
>
> The paper which this design is based on (reference 3 on that open cores
> page) experimentally predicts frequency jitter reduction of ~5-10 fold over
> input jitter on a relatively noisy signal. We are getting approximately 2
> fold reduction, but even if we got the ideal jitter filtering, it would not
> be enough for us. Ideally we want 50-100 fold jitter reduction, but we will
> take anything over 2 fold for now.
>
> When we feed the dpll a essentially jitter free signal (~0.5mHz jitter at
> 700KHz from a very expensive Stanford Research Systems function generator)
> or if we let the dpll run as an open loop we find that the dpll has an
> intrinsic jitter of approximately 2 mHz at 700KHz with a 100MHz clock.
>
> My question is, is there anyway to reduce the output jitter of our DPLL,
> either through some kind of filtering afterwards in the design or perhaps
> something more substantial when it comes to clock choice or output routing
> on the physical board itself.

"Or let the DPLL run as open loop"

Do you mean if you feed a constant to your NCO, whatever that may be? 
If that's the case, then your problem is your reference clock.  This is 
backed up by your results with that Stanford Research Systems function 
generator -- your DPLL will see it's reference clock as "truth" even if 
it's jittery.  Give it a jittery reference clock and feed it the World's 
Cleanest Signal as input and it'll see jitter in that input and "clean" 
it right up.

What are you clocking your chip with?  Are you sure it's clean?  Are you 
sure it's clean after your FPGA gets done with it?

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

To begin with: FPGA doesn't mate with low jitter. No matter what 
filtering is, you can expect jitter in ~100ps range, due to coupling on 
the crystal. This is rather poor performance. If you need better then 
that, do a specialized analog circuit.

Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com


crasic wrote:
> Hi all.
> 
> We are using a DPLL synthesized in an FPGA as a tracking bandpass filter.
> The PLL design is based on some older IEEE papers (late 70's) and uses a
> binary phase detector and a sequential loop filter (a "Variable Reset
> Random Walk Filter" or "VR-RMF" in dsp jargon), essentially we
> reimplemented this open cores project :
> http://opencores.org/project,dpll_rwf (Boy would it have saved me time to
> have known about his core!) 
> 
> The paper which this design is based on (reference 3 on that open cores
> page) experimentally predicts frequency jitter reduction of ~5-10 fold over
> input jitter on a relatively noisy signal. We are getting approximately 2
> fold reduction, but even if we got the ideal jitter filtering, it would not
> be enough for us. Ideally we want 50-100 fold jitter reduction, but we will
> take anything over 2 fold for now.
> 
> When we feed the dpll a essentially jitter free signal (~0.5mHz jitter at
> 700KHz from a very expensive Stanford Research Systems function generator)
> or if we let the dpll run as an open loop we find that the dpll has an
> intrinsic jitter of approximately 2 mHz at 700KHz with a 100MHz clock. 
> 
> My question is, is there anyway to reduce the output jitter of our DPLL,
> either through some kind of filtering afterwards in the design or perhaps 
> something more substantial when it comes to clock choice or output routing
> on the physical board itself. 
> 
> 
> 
> 

On 06/13/2010 08:54 AM, Vladimir Vassilevsky wrote:
(top posting fixed)

> crasic wrote:
>> Hi all.
>>
>> We are using a DPLL synthesized in an FPGA as a tracking bandpass filter.
>> The PLL design is based on some older IEEE papers (late 70's) and uses a
>> binary phase detector and a sequential loop filter (a "Variable Reset
>> Random Walk Filter" or "VR-RMF" in dsp jargon), essentially we
>> reimplemented this open cores project :
>> http://opencores.org/project,dpll_rwf (Boy would it have saved me time to
>> have known about his core!)
>> The paper which this design is based on (reference 3 on that open cores
>> page) experimentally predicts frequency jitter reduction of ~5-10 fold
>> over
>> input jitter on a relatively noisy signal. We are getting approximately 2
>> fold reduction, but even if we got the ideal jitter filtering, it
>> would not
>> be enough for us. Ideally we want 50-100 fold jitter reduction, but we
>> will
>> take anything over 2 fold for now.
>>
>> When we feed the dpll a essentially jitter free signal (~0.5mHz jitter at
>> 700KHz from a very expensive Stanford Research Systems function
>> generator)
>> or if we let the dpll run as an open loop we find that the dpll has an
>> intrinsic jitter of approximately 2 mHz at 700KHz with a 100MHz clock.
>> My question is, is there anyway to reduce the output jitter of our DPLL,
>> either through some kind of filtering afterwards in the design or
>> perhaps something more substantial when it comes to clock choice or
>> output routing
>> on the physical board itself.
 >
 > To begin with: FPGA doesn't mate with low jitter. No matter what
 > filtering is, you can expect jitter in ~100ps range, due to coupling on
 > the crystal. This is rather poor performance. If you need better then
 > that, do a specialized analog circuit.

You you mean coupling on the semiconductor substrate?

FPGA's make jitter, but I've always assumed it was random noise at the 
gates, rather than noise getting coupled in.

In either case, there is a limit to how well you can do with an FPGA, 
beyond which you have to use more clever circuitry.

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

Tim Wescott wrote:

> On 06/13/2010 08:54 AM, Vladimir Vassilevsky wrote:
> (top posting fixed)
> 

>  > To begin with: FPGA doesn't mate with low jitter. No matter what
>  > filtering is, you can expect jitter in ~100ps range, due to coupling on
>  > the crystal. This is rather poor performance. If you need better then
>  > that, do a specialized analog circuit.
> 
> You you mean coupling on the semiconductor substrate?

Yes. The coupling inside is substantial, and it dominates over other 
sources of disturbance. It is evident if you look at the spectrum.

> FPGA's make jitter, but I've always assumed it was random noise at the 
> gates, rather than noise getting coupled in.
> 
> In either case, there is a limit to how well you can do with an FPGA, 
> beyond which you have to use more clever circuitry.

Signals generated by general purpose digital parts such as CPUs and 
FPGAs have rather poor jitter; I was surprised to see that parts 
advertized as "low jitter clock generators" are usually no better.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

On 06/13/2010 11:38 AM, Vladimir Vassilevsky wrote:
>
>
> Tim Wescott wrote:
>
>> On 06/13/2010 08:54 AM, Vladimir Vassilevsky wrote:
>> (top posting fixed)
>>
>
>> > To begin with: FPGA doesn't mate with low jitter. No matter what
>> > filtering is, you can expect jitter in ~100ps range, due to coupling on
>> > the crystal. This is rather poor performance. If you need better then
>> > that, do a specialized analog circuit.
>>
>> You you mean coupling on the semiconductor substrate?
>
> Yes. The coupling inside is substantial, and it dominates over other
> sources of disturbance. It is evident if you look at the spectrum.
>
>> FPGA's make jitter, but I've always assumed it was random noise at the
>> gates, rather than noise getting coupled in.
>>
>> In either case, there is a limit to how well you can do with an FPGA,
>> beyond which you have to use more clever circuitry.
>
> Signals generated by general purpose digital parts such as CPUs and
> FPGAs have rather poor jitter; I was surprised to see that parts
> advertized as "low jitter clock generators" are usually no better.

The OP needs to cross-post this question over to sci.electronics.design, 
under the heading "low jitter digital circuitry".  Maybe they'll stop 
talking politics long enough to actually make a positive contribution!

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

Vladimir Vassilevsky <nospam@nowhere.com> writes:

> Tim Wescott wrote:
>
>> On 06/13/2010 08:54 AM, Vladimir Vassilevsky wrote:
>> (top posting fixed)
>>
>
>>  > To begin with: FPGA doesn't mate with low jitter. No matter what
>>  > filtering is, you can expect jitter in ~100ps range, due to coupling on
>>  > the crystal. This is rather poor performance. If you need better then
>>  > that, do a specialized analog circuit.
>>
>> You you mean coupling on the semiconductor substrate?
>
> Yes. The coupling inside is substantial, and it dominates over other
> sources of disturbance. It is evident if you look at the spectrum.
>
>> FPGA's make jitter, but I've always assumed it was random noise at
>> the gates, rather than noise getting coupled in.
>>
>> In either case, there is a limit to how well you can do with an
>> FPGA, beyond which you have to use more clever circuitry.
>
> Signals generated by general purpose digital parts such as CPUs and
> FPGAs have rather poor jitter; I was surprised to see that parts
> advertized as "low jitter clock generators" are usually no better.

You came across this in some of your Class D designs, Vladimir?
-- 
Randy Yates                      % "Remember the good old 1980's, when 
Digital Signal Labs              %  things were so uncomplicated?"
mailto://yates@ieee.org          % 'Ticket To The Moon' 
http://www.digitalsignallabs.com % *Time*, Electric Light Orchestra

PS: I found what looks like a great analysis of this
effect:

http://www.imse.cnm.es/esd-msd/WORKSHOPS/IMEC2001/presentations.htm#1a

--Ry

Vladimir Vassilevsky <nospam@nowhere.com> writes:

> Tim Wescott wrote:
>
>> On 06/13/2010 08:54 AM, Vladimir Vassilevsky wrote:
>> (top posting fixed)
>>
>
>>  > To begin with: FPGA doesn't mate with low jitter. No matter what
>>  > filtering is, you can expect jitter in ~100ps range, due to coupling on
>>  > the crystal. This is rather poor performance. If you need better then
>>  > that, do a specialized analog circuit.
>>
>> You you mean coupling on the semiconductor substrate?
>
> Yes. The coupling inside is substantial, and it dominates over other
> sources of disturbance. It is evident if you look at the spectrum.
>
>> FPGA's make jitter, but I've always assumed it was random noise at
>> the gates, rather than noise getting coupled in.
>>
>> In either case, there is a limit to how well you can do with an
>> FPGA, beyond which you have to use more clever circuitry.
>
> Signals generated by general purpose digital parts such as CPUs and
> FPGAs have rather poor jitter; I was surprised to see that parts
> advertized as "low jitter clock generators" are usually no better.
>
>
> Vladimir Vassilevsky
> DSP and Mixed Signal Design Consultant
> http://www.abvolt.com
>

-- 
Randy Yates                      % "My Shangri-la has gone away, fading like 
Digital Signal Labs              %  the Beatles on 'Hey Jude'" 
mailto://yates@ieee.org          %  
http://www.digitalsignallabs.com % 'Shangri-La', *A New World Record*, ELO

>"Or let the DPLL run as open loop"
>
>Do you mean if you feed a constant to your NCO, whatever that may be? 
>If that's the case, then your problem is your reference clock.  This is 
>backed up by your results with that Stanford Research Systems function 
>generator -- your DPLL will see it's reference clock as "truth" even if 
>it's jittery.  Give it a jittery reference clock and feed it the World's 
>Cleanest Signal as input and it'll see jitter in that input and "clean" 
>it right up.

>Tim Wescott
>Control system and signal processing consulting
>www.wescottdesign.com
>


This DPLL design runs at a frequency set at with an output divider, it is
essentially a pulse-steal design that adds or subtracts fast clock pulses
to the base frequency. The capture range for a 100MHz clock is
approximately 0.1f_set so with the center frequency of ~700Khz we get a
8Khz bandpass. 

If the signal is outside the lockrange or there is no signal applied the
pll runs at its open loop frequency set by the divider.




>To begin with: FPGA doesn't mate with low jitter. No matter what 
>filtering is, you can expect jitter in ~100ps range, due to coupling on 
>the crystal. This is rather poor performance. If you need better then 
>that, do a specialized analog circuit.
>
>Vladimir Vassilevsky
>DSP and Mixed Signal Design Consultant
>http://www.abvolt.com


The end design will have some additional digital circuitry on the board in
the form of an ADC and control circuitry so if there are any digital
non-fpga solutions that could supplement our fpga filter I'm open to it. We
are trying to replace specialized (power hungry and expensive as well!)
analog circuitry with a digital solution so going back to it would be
pretty redundant!

Could we potentially expect better performance with a programmable logic
chip instead of an FPGA?

The clock source is a generic crystal generator. Unfortunately I didn't
have the chance to measure the clock jitter and measuring it now through
the fpga results in some crazy readings (~1hz at 50 Mhz, or 100 times worse
than our pll output jitter)

Randy Yates wrote:

> Vladimir Vassilevsky <nospam@nowhere.com> writes:
> 

>>Signals generated by general purpose digital parts such as CPUs and
>>FPGAs have rather poor jitter; I was surprised to see that parts
>>advertized as "low jitter clock generators" are usually no better.
> 
> You came across this in some of your Class D designs, Vladimir?


Thanks for the link. Interesting reading; although in the real world 
they rarely give out *any* jitter specs for digital parts. Yes, jitter 
is crucial in Class D; and this is one of the reasons why naive digital 
amplifiers have mediocre performance. Other area where it matters is the 
RF signal generation.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com