Phase-frequency detector with synchronous output?

I'm looking at ways of implementing a PLL (minus the VCXO) entirely in
an FPGA. Our traditional approach has been to have PFD in the FPGA,
take the up/down pulses and run them into an external charge pump-
>filter->VCXO. I would like to move everything up to the VCXO inside
the FPGA (naturally there ould be a D-A involved to drive the external
VCXO).

The particular part of this problem that I'm trying to wrap my head
around is how to deal with the PFD. The filter would ideally run at a
fixed sampling frequency that is unrelated to the reference or
feedback into the PFD. If I simply sample the up/down pulses onto a
fast clock (i.e. the filter sampling clock), into an accumulator, to
generate an error signal, I would get some feedback from the sampling
frequency into the resulting error signal. This would result in
unwanted components going to the filter, the VCXO, etc.) How can I
avoid/minimize this?

For reference - feedback/reference frequencies are in the tens of kHz
range, VCXO frequencies are in the 50-150MHz range, and available
clocks to drive FPGA logic (filter sampling clock) can be up to about
200MHz. Loop filter bandwidth is in the 5-50Hz range, output jitter
tolerance is low.

All digital PLLs are a new thing for me, so please bear with me.

Thanks,

Chris

On 6/24/2010 9:32 AM, Chris Maryan wrote:
> I'm looking at ways of implementing a PLL (minus the VCXO) entirely in
> an FPGA. Our traditional approach has been to have PFD in the FPGA,
> take the up/down pulses and run them into an external charge pump-
>> filter->VCXO. I would like to move everything up to the VCXO inside
> the FPGA (naturally there ould be a D-A involved to drive the external
> VCXO).
>
> The particular part of this problem that I'm trying to wrap my head
> around is how to deal with the PFD. The filter would ideally run at a
> fixed sampling frequency that is unrelated to the reference or
> feedback into the PFD. If I simply sample the up/down pulses onto a
> fast clock (i.e. the filter sampling clock), into an accumulator, to
> generate an error signal, I would get some feedback from the sampling
> frequency into the resulting error signal. This would result in
> unwanted components going to the filter, the VCXO, etc.) How can I
> avoid/minimize this?
>
> For reference - feedback/reference frequencies are in the tens of kHz
> range, VCXO frequencies are in the 50-150MHz range, and available
> clocks to drive FPGA logic (filter sampling clock) can be up to about
> 200MHz. Loop filter bandwidth is in the 5-50Hz range, output jitter
> tolerance is low.
>
> All digital PLLs are a new thing for me, so please bear with me.
>
> Thanks,
>
> Chris

Is there a particular reason you want to do this?  The simplest loop 
filter is just an R/C off of one FPGA pin using push-pull drive, tiny 
and almost free.  I've had better luck using two FPGA pins with tristate 
drive and an op-amp integrator; that takes 2 resistors to create Vcc/2, 
1 resistor and one cap for the loop filter.  That's still pretty small, 
and still decently cheap.

If you start getting into the idea of using a DAC to drive the VCXO 
you're likely to start piling costs on well in excess of the $1 for the 
op-amp based LF.  You'll need more engineering, more FPGA pins, and more 
money to do it.

Go give a look at Xilinx app note XAPP250: Clock and Data Recovery with 
Coded Data Streams, and check out their PLL implementation.  Unless 
you're looking to have some sort of fancy non-linear LF algorithm, 
analog PLL implementations still have some real merits.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Chris Maryan wrote:

> I'm looking at ways of implementing a PLL (minus the VCXO) entirely in
> an FPGA. Our traditional approach has been to have PFD in the FPGA,
> take the up/down pulses and run them into an external charge pump-
> 
>>filter->VCXO. I would like to move everything up to the VCXO inside 
> the FPGA (naturally there ould be a D-A involved to drive the external
> VCXO).
> 
> The particular part of this problem that I'm trying to wrap my head
> around is how to deal with the PFD. The filter would ideally run at a
> fixed sampling frequency that is unrelated to the reference or
> feedback into the PFD. If I simply sample the up/down pulses onto a
> fast clock (i.e. the filter sampling clock), into an accumulator, to
> generate an error signal, I would get some feedback from the sampling
> frequency into the resulting error signal. This would result in
> unwanted components going to the filter, the VCXO, etc.) How can I
> avoid/minimize this?
> 
> For reference - feedback/reference frequencies are in the tens of kHz
> range, VCXO frequencies are in the 50-150MHz range, and available
> clocks to drive FPGA logic (filter sampling clock) can be up to about
> 200MHz. Loop filter bandwidth is in the 5-50Hz range, output jitter
> tolerance is low.
> 
> All digital PLLs are a new thing for me, so please bear with me.

A phase detector inputs two asynchronous clocks. Connecting two 
asynchronous domains in FPGA is (almost always) not a good idea.

I would use an input-capture type of logic. This gives the 
phase/frequency error with the resolution of one system clock.  Then I 
filter it digitally, apply to DAC and finally filter it by an analog RC.

When the lock is acquired, there will be a loop limit cycle behavior 
with the phase drifting back and forth by +/- 1 system clock. The 
intelligent algorithm should gradually adjust the parameters of the loop 
so the phase sliding due to the limit cycle of the loop will be about 
the same as the drift of the oscillator on the period of the limit cycle.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

On 06/24/2010 09:32 AM, Chris Maryan wrote:
> I'm looking at ways of implementing a PLL (minus the VCXO) entirely in
> an FPGA. Our traditional approach has been to have PFD in the FPGA,
> take the up/down pulses and run them into an external charge pump-
>> filter->VCXO. I would like to move everything up to the VCXO inside
> the FPGA (naturally there ould be a D-A involved to drive the external
> VCXO).
>
> The particular part of this problem that I'm trying to wrap my head
> around is how to deal with the PFD. The filter would ideally run at a
> fixed sampling frequency that is unrelated to the reference or
> feedback into the PFD. If I simply sample the up/down pulses onto a
> fast clock (i.e. the filter sampling clock), into an accumulator, to
> generate an error signal, I would get some feedback from the sampling
> frequency into the resulting error signal. This would result in
> unwanted components going to the filter, the VCXO, etc.) How can I
> avoid/minimize this?
>
> For reference - feedback/reference frequencies are in the tens of kHz
> range, VCXO frequencies are in the 50-150MHz range, and available
> clocks to drive FPGA logic (filter sampling clock) can be up to about
> 200MHz. Loop filter bandwidth is in the 5-50Hz range, output jitter
> tolerance is low.
>
> All digital PLLs are a new thing for me, so please bear with me.

I'm not sure that you can get there from here.  One of the real 
advantages to an asynchronous PFD is that its resolution is essentially 
infinite.  You'll have other sources of noise, but the quantization 
noise will be exactly nil.

OTOH, you're proposing a system that has a guaranteed minimum 
quantization noise in the PFD of +/- 2.5ps.  At an output frequency of 
100MHz, that's 90 degrees of phase jitter.  You may be able to 
ameliorate this noise to an astounding degree with clever use of jitter 
on the input side, but even if you can get the contribution from 
quantization noise stomped well below the noise floor, you'll do so at 
the cost of analog circuitry on the outside of the chip.

The cheapest way that I can see to add this jitter would be to vary the 
threshold of whatever comparator you're using to capture the VXCO signal 
-- but you need to vary that threshold cleanly over 90 degrees, in a way 
that insures that the resulting phase jitter is as high a frequency as 
possible, with as few low-frequency components as manageable.  So it 
ain't going to be easy!

If you're really lucky those digital delay lines that Xilinx (assuming 
it's a Xilinx chip) builds into their chips can be actively diddled with 
and are well behaved, and you'll be able to jitter the reference or the 
VXCO signal there.

Get that dealt with, though, and I think you'll be OK -- just make the 
PFD integrating.  IOW, take the output of the PFD and use it twiddle a 
counter -- increment, decrement, or leave alone.  Then your PFD will act 
as an integrator with a known gain, and any really high frequency 
components will be washed out.  Now follow that not with the usual PI 
loop filter, but with a PD, with a carefully limited bandwidth on the 
differentiator (and possibly with a leading low-pass filter or three).

You'll still have to do some careful analysis of how the loop will 
respond to the asynchronous sampling, but you may actually get there 
from here on this part of it.  When you do the analysis you'll find that 
when you're in perfect lock the asynchronous sampling of the PFD won't 
matter at all, because its output will be zero.  So to shine a light on 
that issue you'll want to analyze the phase noise of the loop when it's 
tracking a ramp input, or to noise on the reference.

I wouldn't even think of introducing such a PLL in a product unless I 
knew the issues, knew how to model each part of the system, and had done 
a careful noise analysis that showed that I was going to beat the 
desired output noise specification by a really good margin (I'd want at 
least 4:1 going in).  This sort of thing always has more error sources 
than you think, so you want to make sure that anything that you're doing 
is trivial compared to your final desired output.

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

Tim Wescott wrote:


> You'll still have to do some careful analysis of how the loop will 
> respond to the asynchronous sampling, but you may actually get there 
> from here on this part of it.  When you do the analysis you'll find that 
> when you're in perfect lock the asynchronous sampling of the PFD won't 
> matter at all, because its output will be zero.

Balancing on the razor edge. In practice, there will be either a dead 
band or an area of the extreme sensitivity to all kinds of noise and 
interferrence.

VLV

On 06/24/2010 10:54 AM, Vladimir Vassilevsky wrote:
>
>
> Tim Wescott wrote:
>
>
>> You'll still have to do some careful analysis of how the loop will
>> respond to the asynchronous sampling, but you may actually get there
>> from here on this part of it. When you do the analysis you'll find
>> that when you're in perfect lock the asynchronous sampling of the PFD
>> won't matter at all, because its output will be zero.
>
> Balancing on the razor edge. In practice, there will be either a dead
> band or an area of the extreme sensitivity to all kinds of noise and
> interferrence.

No kidding.  Hence the next sentence: "So you'll want to shine a light 
on..."

I suppose I maybe didn't stress that enough -- but can you?

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com