We are designing a circuit in FPGA which has many modules and each operating at different clock frequencies (but,each clock will be multiple of other). each module will be connected to other module in sequential fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) --> Module D (10KHz) --> Module E (20KHz). What are the things do i need to consider while designing such circuits? I use xilinx ISE webpack 12.1 and ISE simulator. Do we have to purchase any other tools for verification of such designs?
multiple clock design
Started by ●July 10, 2010
Reply by ●July 10, 20102010-07-10
san_jack wrote:> We are designing a circuit in FPGA which has many modules and each > operating at different clock frequencies (but,each clock will be multiple > of other). each module will be connected to other module in sequential > fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) --> > Module D (10KHz) --> Module E (20KHz). > > What are the things do i need to consider while designing such circuits?If you are running at kHz speed, consider MCU or DSP instead of FPGA. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●July 10, 20102010-07-10
On 07/10/2010 06:49 AM, Vladimir Vassilevsky wrote:> > > san_jack wrote: >> We are designing a circuit in FPGA which has many modules and each >> operating at different clock frequencies (but,each clock will be multiple >> of other). each module will be connected to other module in sequential >> fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) --> >> Module D (10KHz) --> Module E (20KHz). >> >> What are the things do i need to consider while designing such circuits? > > If you are running at kHz speed, consider MCU or DSP instead of FPGA.No kidding! If there's some reason you can't use a processor, at least consider aggressively trading off space for speed (a processor's a good way to do that if the algorithm is big enough). Or just clock the whole thing at 20kHz, and put registers on the output such that module B only changes every 2nd clock, module C every 10th, etc. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●July 12, 20102010-07-12
I Hope, it should be "Or just clock the whole thing at 2kHz, and put registers on the output such that module B only changes every 5th clock, module A every 10th, etc.". Is my understanding correct?>On 07/10/2010 06:49 AM, Vladimir Vassilevsky wrote: >> >> >> san_jack wrote: >>> We are designing a circuit in FPGA which has many modules and each >>> operating at different clock frequencies (but,each clock will bemultiple>>> of other). each module will be connected to other module in sequential >>> fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) --> >>> Module D (10KHz) --> Module E (20KHz). >>> >>> What are the things do i need to consider while designing suchcircuits?>> >> If you are running at kHz speed, consider MCU or DSP instead of FPGA. > >No kidding! > >If there's some reason you can't use a processor, at least consider >aggressively trading off space for speed (a processor's a good way to do >that if the algorithm is big enough). Or just clock the whole thing at >20kHz, and put registers on the output such that module B only changes >every 2nd clock, module C every 10th, etc. > >-- > >Tim Wescott >Wescott Design Services >http://www.wescottdesign.com > >Do you need to implement control loops in software? >"Applied Control Theory for Embedded Systems" was written for you. >See details at http://www.wescottdesign.com/actfes/actfes.html >
Reply by ●July 12, 20102010-07-12
No, you have missed the idea. If the entire circuit is clocked at 20 kHz, you can generate a signal that is asserted just once in every other clock cycle which will enable the registers in the 10 kHz logic, every other enable generates another enable (once in four clock cycles) for the 5 kHz logic) and another enable asserted once in 10 clocks for the 2 kHz logic. When you use enables on the registers the logic runs as a slower rate, not a faster rate. I don't mean to be pessimistic, but if you don't understand enabled registers, you aren't likely to end up with a working design. Is this a real project or a student exercise? Rick On Jul 12, 1:21�am, "san_jack" <sridar@n_o_s_p_a_m.kphsonline.com> wrote:> I Hope, it should be "Or just clock the whole thing at 2kHz, and put > registers on the output such that module B only changes every 5th clock, > module A every 10th, etc.". Is my understanding correct? > > > > >On 07/10/2010 06:49 AM, Vladimir Vassilevsky wrote: > > >> san_jack wrote: > >>> We are designing a circuit in FPGA which has many modules and each > >>> operating at different clock frequencies (but,each clock will be > multiple > >>> of other). each module will be connected to other module in sequential > >>> fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) --> > >>> Module D (10KHz) --> Module E (20KHz). > > >>> What are the things do i need to consider while designing such > circuits? > > >> If you are running at kHz speed, consider MCU or DSP instead of FPGA. > > >No kidding! > > >If there's some reason you can't use a processor, at least consider > >aggressively trading off space for speed (a processor's a good way to do > >that if the algorithm is big enough). �Or just clock the whole thing at > >20kHz, and put registers on the output such that module B only changes > >every 2nd clock, module C every 10th, etc. > > >-- > > >Tim Wescott > >Wescott Design Services > >http://www.wescottdesign.com > > >Do you need to implement control loops in software? > >"Applied Control Theory for Embedded Systems" was written for you. > >See details athttp://www.wescottdesign.com/actfes/actfes.html > >
Reply by ●July 12, 20102010-07-12
On 07/11/2010 10:21 PM, san_jack wrote: (top posting fixed)>> On 07/10/2010 06:49 AM, Vladimir Vassilevsky wrote: >>> >>> >>> san_jack wrote: >>>> We are designing a circuit in FPGA which has many modules and each >>>> operating at different clock frequencies (but,each clock will be > multiple >>>> of other). each module will be connected to other module in sequential >>>> fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) --> >>>> Module D (10KHz) --> Module E (20KHz). >>>> >>>> What are the things do i need to consider while designing such > circuits? >>> >>> If you are running at kHz speed, consider MCU or DSP instead of FPGA. >> >> No kidding! >> >> If there's some reason you can't use a processor, at least consider >> aggressively trading off space for speed (a processor's a good way to do >> that if the algorithm is big enough). Or just clock the whole thing at >> 20kHz, and put registers on the output such that module B only changes >> every 2nd clock, module C every 10th, etc. >>> I Hope, it should be "Or just clock the whole thing at 2kHz, and put > registers on the output such that module B only changes every 5th > clock, > module A every 10th, etc.". Is my understanding correct? No. You either have to use multiple clock domains or you have to hold the data. If you hold the data, you have to clock the whole chip at the highest clock rate -- not the lowest. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●July 12, 20102010-07-12
On Jul 10, 1:37�am, "san_jack" <sridar@n_o_s_p_a_m.kphsonline.com> wrote:> We are designing a circuit in FPGA which has many modules and each > operating at different clock frequencies (but,each clock will be multiple > of other). each module will be connected to other module in sequential > fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) --> > Module D (10KHz) --> Module E (20KHz). > > What are the things do i need to consider while designing such circuits? > > I use xilinx ISE webpack 12.1 and ISE simulator. Do we have to purchase any > other tools for verification of such designs?Assuming your 2kHz is synchronous to your 20kHz and 10kHz. Just clock the whole thing at 20kHz and run lower rate clock enables where appropriate. Chris
Reply by ●July 13, 20102010-07-13
Hi all, thanks for your quick and useful responses. This ain't a student exercise. Should we have to consider setup and hold time violation while transferring data from high frequency to lower frequency domain.>On Jul 10, 1:37=A0am, "san_jack" <sridar@n_o_s_p_a_m.kphsonline.com> >wrote: >> We are designing a circuit in FPGA which has many modules and each >> operating at different clock frequencies (but,each clock will bemultiple>> of other). each module will be connected to other module in sequential >> fashion. Module A (20KHz) --> Module B (10KHz) --> Module C (2KHz) --> >> Module D (10KHz) --> Module E (20KHz). >> >> What are the things do i need to consider while designing suchcircuits?>> >> I use xilinx ISE webpack 12.1 and ISE simulator. Do we have to purchasea=>ny >> other tools for verification of such designs? > >Assuming your 2kHz is synchronous to your 20kHz and 10kHz. Just clock >the whole thing at 20kHz and run lower rate clock enables where >appropriate. > >Chris >
Reply by ●July 13, 20102010-07-13
The trick is that you aren't transfering things between clock domains,
just between clock enable domains. Everything always runs on the
fastest clock (in your case 20kHz), then you create clock enables
carried on the 20kHz clock, but at 10kHz or 2kHz rates. So when you
define your clocks in ISE, you only define one 20kHz clock and the
timing is valid for all of the clock enable domains.
In VHDL it goes like this:
-- Process for 20kHz stuff
process (clk_20k)
begin
if rising_edge(clk_20k) then
if state = '0' then
clk_en_10k <= '1'; -- generate a 10kHz clock enable
data_to_10k <= stuff; -- take data out of 20kHz process every
other 20kHz clock cycle. data_to_10k is valid for the entire 10kHz
cycle.
else
clk_en_10k <= '0'; -- clock enable is 50% duty cycle of a 20kHz
clock
end if;
state <= not state; -- toggle every other cycle to generate 10k
stuff
-- Do 20kHz stuff
-- generate whatever data you want to send to the 10kHz process
end if;
enc process;
-- Process for 10kHz stuff
process(clk_20k) -- Note that this still runs on the 20kHz clock
begin
if rising_edge(clk_20k) then
if clk_en_10k = '1' then
-- Anything done in this spot runs at 10kHz
-- Do whatever you need to do with data_to_10k
-- subdivide as necessary for 2kHz
end if;
end if;
end process;
Also, as others have pointed out, 20kHz is really slow for an FPGA.
You might consider just using a microcontroller if you're more
comfortable with that.
Chris
On Jul 13, 12:23�am, "san_jack" <sridar@n_o_s_p_a_m.kphsonline.com>
wrote:
> Hi all,
> thanks for your quick and useful responses. This ain't a student exercise.
> Should we have to consider setup and hold time violation while transferring
> data from high frequency to lower frequency domain.
<snip>
> >Assuming your 2kHz is synchronous to your 20kHz and 10kHz. Just clock
> >the whole thing at 20kHz and run lower rate clock enables where
> >appropriate.
>
> >Chris- Hide quoted text -
>
> - Show quoted text -
Reply by ●July 13, 20102010-07-13
On 7/13/2010 9:41 AM, Chris Maryan wrote:> The trick is that you aren't transfering things between clock domains, > just between clock enable domains. Everything always runs on the > fastest clock (in your case 20kHz), then you create clock enables > carried on the 20kHz clock, but at 10kHz or 2kHz rates. So when you > define your clocks in ISE, you only define one 20kHz clock and the > timing is valid for all of the clock enable domains. > > In VHDL it goes like this:... In any case, setup and hold times depend on the device, not the speed that it's clocked at. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
