Hello,
Are there any applications where we need to generate
sinusoidal locked loop which will be in phase and
frequency lock with incoming sine wave?
If so than how to design one? Can we use 2nd Order IIR's
and vary their coefficients in some way to generate the
sinusiod?
Regards
Bharat
digital sinusoidal locked loop?
Started by ●October 10, 2010
Reply by ●October 10, 20102010-10-10
>Hello, > > Are there any applications where we need to generate > sinusoidal locked loop which will be in phase and > frequency lock with incoming sine wave? > > If so than how to design one? Can we use 2nd Order IIR's > and vary their coefficients in some way to generate the > sinusiod? > >Regards >Bharat >Carrier tracking at receiver is just a case of what you are describing. It can be done fully digitally using feedback based derotation depending on a phase error algorithm
Reply by ●October 10, 20102010-10-10
On Sun, 10 Oct 2010 01:30:58 -0500, "bharat pathak" <bharat@n_o_s_p_a_m.arithos.com> wrote:>Hello, > > Are there any applications where we need to generate > sinusoidal locked loop which will be in phase and > frequency lock with incoming sine wave? > > If so than how to design one? Can we use 2nd Order IIR's > and vary their coefficients in some way to generate the > sinusiod? > >Regards >BharatIt sounds to me like you're describing a traditional Phase Locked Loop. Locking two sine waves together to generate either a more stable output or an output at a different frequency is very common. Eric Jacobsen Minister of Algorithms Abineau Communications http://www.abineau.com
Reply by ●October 10, 20102010-10-10
On Oct 10, 7:30�pm, "bharat pathak" <bharat@n_o_s_p_a_m.arithos.com> wrote:> Hello, > > � � �Are there any applications where we need to generate > � � �sinusoidal locked loop which will be in phase and > � � �frequency lock with incoming sine wave? > > � � �If so than how to design one? Can we use 2nd Order IIR's > � � �and vary their coefficients in some way to generate the > � � �sinusiod? > > Regards > Bharathttp://groups.google.co.nz/group/comp.dsp/browse_thread/thread/47b8039554d419ed/4a85c4f0404c0f0e?hl=en&q=matlab+pll#4a85c4f0404c0f0e
Reply by ●October 10, 20102010-10-10
On 10/09/2010 11:30 PM, bharat pathak wrote:> Hello, > > Are there any applications where we need to generate > sinusoidal locked loop which will be in phase and > frequency lock with incoming sine wave?Yes, although in the digital world it's much more common to separate the task into synchronizing some clock to an incoming sine wave, then generating a sine wave synchronized to that clock.> If so than how to design one?Do a web search on "phase locked loop"> Can we use 2nd Order IIR's > and vary their coefficients in some way to generate the > sinusiod?Yes, and I believe that it's been done with at least one DDS chip. If you have a system who's characteristic polynomial is P = z^2 - 2 * (cos th) * z + 1 + a with a = 0 then it'll oscillate with a frequency of th radians/step, forever. You can use that as an NCO by varying th as necessary for frequency changes, and maintain amplitude by varying a as an AGC element (there are other ways to maintain amplitude). But there are other, more direct, not terribly more expensive ways to do DDS that don't involve nonlinear, low-distortion (and therefore arcane) IIR systems. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●October 10, 20102010-10-10
Eric Jacobsen <eric.jacobsen@ieee.org> wrote:> On Sun, 10 Oct 2010 01:30:58 -0500, "bharat pathak" > <bharat@n_o_s_p_a_m.arithos.com> wrote:>> Are there any applications where we need to generate >> sinusoidal locked loop which will be in phase and >> frequency lock with incoming sine wave?(snip)> It sounds to me like you're describing a traditional Phase Locked > Loop. Locking two sine waves together to generate either a more > stable output or an output at a different frequency is very common.I thought the usual PLL generates a square wave in the VCO, and uses that for the phase comparator. I thought the OP wanted a sine into the phase comparator. -- glen
Reply by ●October 10, 20102010-10-10
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:i8t5bt$ks5$1@speranza.aioe.org...> I thought the OP wanted > a sine into the phase comparator.That's fairly straightforward to do. One example would be a conventional tv color decoder, where the subcarrier is regenerated from a sampled color burst. The whole system is sampled asynchronously to subcarrier, and the subcarrier is generated by a DDS and a ROM. Here's a link to a system I worked on over thirty years ago. http://www.bbc.co.uk/rd/publications/rdreport_1986_02.shtml Pete
Reply by ●October 10, 20102010-10-10
On Sun, 10 Oct 2010 19:49:17 +0000 (UTC), glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:>Eric Jacobsen <eric.jacobsen@ieee.org> wrote: >> On Sun, 10 Oct 2010 01:30:58 -0500, "bharat pathak" >> <bharat@n_o_s_p_a_m.arithos.com> wrote: > >>> Are there any applications where we need to generate >>> sinusoidal locked loop which will be in phase and >>> frequency lock with incoming sine wave? >(snip) > >> It sounds to me like you're describing a traditional Phase Locked >> Loop. Locking two sine waves together to generate either a more >> stable output or an output at a different frequency is very common. > >I thought the usual PLL generates a square wave in the VCO, >and uses that for the phase comparator. I thought the OP wanted >a sine into the phase comparator.Converting a sine to a square wave is a "simple?" comparator, no? If you need a sine wave output, you can use a sine output VCO instead of a square wave VCO too. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
Reply by ●October 11, 20102010-10-11
On Oct 11, 10:27=A0am, Muzaffer Kal <k...@dspia.com> wrote:> On Sun, 10 Oct 2010 19:49:17 +0000 (UTC), glen herrmannsfeldt > > > > <g...@ugcs.caltech.edu> wrote: > >Eric Jacobsen <eric.jacob...@ieee.org> wrote: > >> On Sun, 10 Oct 2010 01:30:58 -0500, "bharat pathak" > >> <bharat@n_o_s_p_a_m.arithos.com> wrote: > > >>> =A0 =A0 Are there any applications where we need to generate > >>> =A0 =A0 sinusoidal locked loop which will be in phase and > >>> =A0 =A0 frequency lock with incoming sine wave? > >(snip) > > >> It sounds to me like you're describing a traditional Phase Locked > >> Loop. =A0 Locking two sine waves together to generate either a more > >> stable output or an output at a different frequency is very common. > > >I thought the usual PLL generates a square wave in the VCO, > >and uses that for the phase comparator. =A0I thought the OP wanted > >a sine into the phase comparator. > > Converting a sine to a square wave is a "simple?" comparator, no?Well yes, for a clean signal but not when there is additive noise. The additive noise gets translated into phase noise in some way.
Reply by ●October 12, 20102010-10-12
On Mon, 11 Oct 2010 12:40:54 -0700 (PDT), HardySpicer <gyansorova@gmail.com> wrote:>On Oct 11, 10:27�am, Muzaffer Kal <k...@dspia.com> wrote: >> On Sun, 10 Oct 2010 19:49:17 +0000 (UTC), glen herrmannsfeldt >> >> >> >> <g...@ugcs.caltech.edu> wrote: >> >Eric Jacobsen <eric.jacob...@ieee.org> wrote: >> >> On Sun, 10 Oct 2010 01:30:58 -0500, "bharat pathak" >> >> <bharat@n_o_s_p_a_m.arithos.com> wrote: >> >> >>> � � Are there any applications where we need to generate >> >>> � � sinusoidal locked loop which will be in phase and >> >>> � � frequency lock with incoming sine wave? >> >(snip) >> >> >> It sounds to me like you're describing a traditional Phase Locked >> >> Loop. � Locking two sine waves together to generate either a more >> >> stable output or an output at a different frequency is very common. >> >> >I thought the usual PLL generates a square wave in the VCO, >> >and uses that for the phase comparator. �I thought the OP wanted >> >a sine into the phase comparator. >> >> Converting a sine to a square wave is a "simple?" comparator, no? > >Well yes, for a clean signal but not when there is additive noise. The >additive noise gets translated into phase noise in some way.How is that any different for a "square wave" signal with non-zero rise time? The phase dedector in question will try to measure when the input goes above a certain voltage level at which point the same noise will be involved in this decision. One of the reasons one implements a PLL is to reject this (usually) high frequency noise and get a clean clock with the same average frequency as the input. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
