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ADC Interpolation Gain

Started by pacman101 February 24, 2011
If I were doing supersampling (or subsampling) how do I know what is the
highest frequency an ADC can subsample?  I am talking the true frequency of
interest, not the images.

Where can I see examples of these designs?

Thanks.

>On Thu, 24 Feb 2011 14:07:06 -0800, Tim Wescott <tim@seemywebsite.com> >wrote: > >>On 02/24/2011 12:39 PM, pacman101 wrote: >>> Thanks. All your comments make sense. I wanted to make sure that I am
on
>>> the right track since I have no experience dealing with playing with
A/D
>>> converters (except using a spectrum analyzer and some readily built >>> radios). >>> >>> So if I were to design an RF receiver, what design parameters should I
pay
>>> particular attention to when choosing the correct ADC? For instance I >>> would think for my application I need high dynamic range and low
jitter,
>>> but what else should I pay attention to so that I don't get screwed by
the
>>> manufacturer? >>> >> >> context snipped << >> >>Look for converters that specify their 2nd- and 3rd-order >>intermodulation distortion -- this is a good indication of the 'useful' >>linearity in a receiver where you may be bringing a much wider band to >>the ADC than you will be sorting out after conversion. >> >>Actually, in general, you want to look for converters that are specified
>>in 'radioish' terms, and the 3rd-order intermod is just part of that. >>This has been a frustration in the past when I was helping to select a >>good ADC for video use, and had to translate (or just plain guess at) >>what the radio-centric specifications meant in terms of a broadband >>signal that went all the way down to DC. >> >>Rate converter noise by spectral height in real frequency -- i.e., take >>the sampling rate into account. >> >>Jitter is important, but shows up as phase noise in your receiver -- >>i.e., if the sampling instant jitters, then a strong signal adjacent to >>a desired weak signal will smear, and will degrade the effective SNR of >>your desired signal. >> >>Note, too, that the ADC jitter is going to specified assuming a perfect >>clock to the ADC -- you can screw this over really quick by not paying >>strict attention to your clock signal. You need to treat the clock to >>the ADC as a precious resource: I know that digital radio guys don't let
>>their ADC clocks go through their FPGAs, because they know the FPGA >>internal noise will mess up their clocks. On the other hand, don't over
>>buy -- there's no point in getting the World's Lowest Jitter ADC if you >>_are_ corrupting your clock's phase noise generating it through an FPGA. >> >>I don't know what else specific to say -- the ADC is one of the choke >>points on performance, so there's a lot of value in modeling your >>receiver's performance parametrically, then plugging a lot of ADC >>parameters into it to see which one really is best. Then look at what >>each ADC needs for care and feeding, and decide how much it's going to >>cost to keep each one happy. >> >>-- >> >>Tim Wescott >>Wescott Design Services >>http://www.wescottdesign.com >> >>Do you need to implement control loops in software? >>"Applied Control Theory for Embedded Systems" was written for you. >>See details at http://www.wescottdesign.com/actfes/actfes.html > >In addition to Tim's points on clock jitter, etc., another parameter >that may be useful in an RF system is the aperture jitter or aperture >delay. This is the jitter in the Sample-and-Hold Amplifier prior to >the ADC and comes into play mostly if you're doing IF-sampling, >sub-sampling or super-Nyquist conversion (i.e., capturing an aliased >image rather than energy within the traditional Nyquist sampling >range). > >And if what you're really getting at is whether it is possible to >collect and process a signal that is WAY down in the dynamic range of >the ADC, then, yes, you can, if you're careful about what you do and >make use of processing gain to isolate and recover it. There are >practical examples of receivers that are pretty old designs that pull >relatively narrow-band PSK signals that occupy about 1-LSB (or a >little less) of a single ADC (i.e., IF sampled) and process them with >barely measurable implementation loss. > >Processing gain is a nice magic trick that a lot of people don't fully >exploit. > > >Eric Jacobsen >http://www.ericjacobsen.org >http://www.dsprelated.com/blogs-1//Eric_Jacobsen.php >
On 02/25/2011 11:17 AM, pacman101 wrote:
(top posting fixed)
>> On Thu, 24 Feb 2011 14:07:06 -0800, Tim Wescott<tim@seemywebsite.com> >> wrote: >> >>> On 02/24/2011 12:39 PM, pacman101 wrote: >>>> Thanks. All your comments make sense. I wanted to make sure that I am > on >>>> the right track since I have no experience dealing with playing with > A/D >> snip << >>> >> In addition to Tim's points on clock jitter, etc., another parameter >> that may be useful in an RF system is the aperture jitter or aperture >> delay. This is the jitter in the Sample-and-Hold Amplifier prior to >> the ADC and comes into play mostly if you're doing IF-sampling, >> sub-sampling or super-Nyquist conversion (i.e., capturing an aliased >> image rather than energy within the traditional Nyquist sampling >> range). >> >> And if what you're really getting at is whether it is possible to >> collect and process a signal that is WAY down in the dynamic range of >> the ADC, then, yes, you can, if you're careful about what you do and >> make use of processing gain to isolate and recover it. There are >> practical examples of receivers that are pretty old designs that pull >> relatively narrow-band PSK signals that occupy about 1-LSB (or a >> little less) of a single ADC (i.e., IF sampled) and process them with >> barely measurable implementation loss. >> >> Processing gain is a nice magic trick that a lot of people don't fully >> exploit. >> >> >> Eric Jacobsen >> http://www.ericjacobsen.org >> http://www.dsprelated.com/blogs-1//Eric_Jacobsen.php >>
> If I were doing supersampling (or subsampling) how do I know what is the > highest frequency an ADC can subsample? I am talking the true frequency of > interest, not the images. > > Where can I see examples of these designs? The two most important parameters that I can think of are the bandwidth of the sample-and-hold front end within the ADC, and the total jitter (aperture and clock) both inside and outside the ADC. The one will kill your signal strength without touching your noise, the other will act like phase noise, spreading out both your signal and interfering signals. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html