ADC design and FPGA clocking (timing)

Hello all,

I started studying ADC design and FPGA clocking and I have a lot of
questions.

I would like to know if small signals that is in between the voltage
full-scale measurement range digitized with the same amount of resolution? 
If it isn't so, is there a way such that the ADC is designed so that no
matter what the input amplitude is, the adc always digitizes it at full (or
near full to avoid saturation) resolution (ie vary the reference voltage to
the ADC)?

As for the interface between ADC and FPGA, if the ADC is running at 150
MHz, at what clock frequency does the FIFO have to be (I believe it is
going to be the same thing).  

Can DSP blocks inside an FPGA be higher (or lower) than the input?  For
instance if I create a 2x upsampling block, followed by a low-pass filter,
then 2x decimation (I'm just making stuff up) can they run at different
frequencies?

Does it makes sense for an FPGA run at its maximum frequency, higher than
the ADC frequency?  

Thank you for your inputs.

On 03/23/2011 09:43 AM, pacman101 wrote:
> Hello all,
>
> I started studying ADC design and FPGA clocking and I have a lot of
> questions.
>
> I would like to know if small signals that is in between the voltage
> full-scale measurement range digitized with the same amount of resolution?

So, for instance, if full range is 2.5V, then can you convert a 1V 
signal with the full resolution of the ADC?

How?  You need the ADC to know that the signal is at 1V, then you need 
to -- well, you get the idea.

> If it isn't so, is there a way such that the ADC is designed so that no
> matter what the input amplitude is, the adc always digitizes it at full (or
> near full to avoid saturation) resolution (ie vary the reference voltage to
> the ADC)?

In theory you can do this.  In practice, many stages in the ADC are 
sensitive to absolute voltage differences rather than ratiometric ones. 
  Noise and offsets, in particular, are going to be in volts (or amps), 
not in proportions of the full range.  So if you measure thingsn in ADC 
counts, then your noise and offset would certainly go up, and I would 
expect your integral and differential nonlinearities to go up, too.

> As for the interface between ADC and FPGA, if the ADC is running at 150
> MHz, at what clock frequency does the FIFO have to be (I believe it is
> going to be the same thing).

If the ADC is _converting_ 150 Msps (mega samples/sec), then the FIFO 
needs to be able to accept that.  For most FPGAs this means clocking the 
FIFO logic with a minimum of 150MHz.

> Can DSP blocks inside an FPGA be higher (or lower) than the input?  For
> instance if I create a 2x upsampling block, followed by a low-pass filter,
> then 2x decimation (I'm just making stuff up) can they run at different
> frequencies?

Yes they can.  Running more than one clock domain in an FPGA means that 
you have to pay careful attention to the signals that cross those clock 
domains -- but it not only can be done, it is often done.

> Does it makes sense for an FPGA run at its maximum frequency, higher than
> the ADC frequency?

FPGAs don't really have "maximum frequencies".  They have a number of 
different delays for various paths in the device (short paths generally 
being faster than long ones, kind of).  So vendors sell them in "speed 
grades", and what clock frequencies can be reliably attained with a 
particular part is heavily dependent on the details of the design.

Usually when an FPGA vendor advertises an FPGA speed it's because 
they've benchmarked the thing with some application that is inherently a 
good fit for the part, which lets them advertise the highest clock they can.

It may indeed make sense for an FPGA to run at a higher frequency than 
the ADC (and perhaps to run all the FPGA at a high frequency, to avoid 
multiple clock domains).  But the higher you push the frequency of 
operation, the harder it will be for the design to meet timing. 
Consistently reaching timing closure with an aggressively fast FPGA 
design is one of the things that separates the men from the boys when it 
comes to FPGA design.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

pacman101 <janpac01@n_o_s_p_a_m.yahoo.com> wrote:
 
> I started studying ADC design and FPGA clocking and I have a lot of
> questions.
 
> I would like to know if small signals that is in between the voltage
> full-scale measurement range digitized with the same amount of resolution? 
> If it isn't so, is there a way such that the ADC is designed so that no
> matter what the input amplitude is, the adc always digitizes it at full (or
> near full to avoid saturation) resolution (ie vary the reference voltage to
> the ADC)?

In the case of DVMs (Digital Volt Meters) this is called autoranging.
It was rare for analog meters, but is common for digital meters.

It takes some time, and normally comes in discrete steps.

In audio systems, it is called AGC or ALC, Automatic (Gain or Level)
Control.  In this case, unlike the DVM case, one is less concerned
with absolute level, and more with the variation of the signal.

Consider those two, and compare to the problem you are working on.

-- glen

Could you please explain to me exactly what FPGA experts mean by timing or
timing closure?

Does it have to do with the fact that in reality there are delays as
signals pass through the logic circuits?  

Also, I do not understand how a dsp block processes data rates faster than
the input.  So say there is a 150 MHz input coming in and I generate a
low-pass filter that runs at 200 Mhz, I would think that at the output at
certain cycles there is nothing coming out since there isn't enough data
coming in.  Am I visualizing this correctly?

>On 03/23/2011 09:43 AM, pacman101 wrote:
>> Hello all,
>>
>> I started studying ADC design and FPGA clocking and I have a lot of
>> questions.
>>
>> I would like to know if small signals that is in between the voltage
>> full-scale measurement range digitized with the same amount of
resolution?
>
>So, for instance, if full range is 2.5V, then can you convert a 1V 
>signal with the full resolution of the ADC?
>
>How?  You need the ADC to know that the signal is at 1V, then you need 
>to -- well, you get the idea.
>
>> If it isn't so, is there a way such that the ADC is designed so that no
>> matter what the input amplitude is, the adc always digitizes it at full
(or
>> near full to avoid saturation) resolution (ie vary the reference voltage
to
>> the ADC)?
>
>In theory you can do this.  In practice, many stages in the ADC are 
>sensitive to absolute voltage differences rather than ratiometric ones. 
>  Noise and offsets, in particular, are going to be in volts (or amps), 
>not in proportions of the full range.  So if you measure thingsn in ADC 
>counts, then your noise and offset would certainly go up, and I would 
>expect your integral and differential nonlinearities to go up, too.
>
>> As for the interface between ADC and FPGA, if the ADC is running at 150
>> MHz, at what clock frequency does the FIFO have to be (I believe it is
>> going to be the same thing).
>
>If the ADC is _converting_ 150 Msps (mega samples/sec), then the FIFO 
>needs to be able to accept that.  For most FPGAs this means clocking the 
>FIFO logic with a minimum of 150MHz.
>
>> Can DSP blocks inside an FPGA be higher (or lower) than the input?  For
>> instance if I create a 2x upsampling block, followed by a low-pass
filter,
>> then 2x decimation (I'm just making stuff up) can they run at different
>> frequencies?
>
>Yes they can.  Running more than one clock domain in an FPGA means that 
>you have to pay careful attention to the signals that cross those clock 
>domains -- but it not only can be done, it is often done.
>
>> Does it makes sense for an FPGA run at its maximum frequency, higher
than
>> the ADC frequency?
>
>FPGAs don't really have "maximum frequencies".  They have a number of 
>different delays for various paths in the device (short paths generally 
>being faster than long ones, kind of).  So vendors sell them in "speed 
>grades", and what clock frequencies can be reliably attained with a 
>particular part is heavily dependent on the details of the design.
>
>Usually when an FPGA vendor advertises an FPGA speed it's because 
>they've benchmarked the thing with some application that is inherently a 
>good fit for the part, which lets them advertise the highest clock they
can.
>
>It may indeed make sense for an FPGA to run at a higher frequency than 
>the ADC (and perhaps to run all the FPGA at a high frequency, to avoid 
>multiple clock domains).  But the higher you push the frequency of 
>operation, the harder it will be for the design to meet timing. 
>Consistently reaching timing closure with an aggressively fast FPGA 
>design is one of the things that separates the men from the boys when it 
>comes to FPGA design.
>
>-- 
>
>Tim Wescott
>Wescott Design Services
>http://www.wescottdesign.com
>
>Do you need to implement control loops in software?
>"Applied Control Theory for Embedded Systems" was written for you.
>See details at http://www.wescottdesign.com/actfes/actfes.html
>

On 03/23/2011 01:45 PM, pacman101 wrote:
(top posting fixed)
>> On 03/23/2011 09:43 AM, pacman101 wrote:
>>> Hello all,
>>>
>>> I started studying ADC design and FPGA clocking and I have a lot of
>>> questions.
>>>
>>> I would like to know if small signals that is in between the voltage
>>> full-scale measurement range digitized with the same amount of
> resolution?
>>
>> So, for instance, if full range is 2.5V, then can you convert a 1V
>> signal with the full resolution of the ADC?
>>
>> How?  You need the ADC to know that the signal is at 1V, then you need
>> to -- well, you get the idea.
>>
>>> If it isn't so, is there a way such that the ADC is designed so that no
>>> matter what the input amplitude is, the adc always digitizes it at full
> (or
>>> near full to avoid saturation) resolution (ie vary the reference voltage
> to
>>> the ADC)?
>>
>> In theory you can do this.  In practice, many stages in the ADC are
>> sensitive to absolute voltage differences rather than ratiometric ones.
>>   Noise and offsets, in particular, are going to be in volts (or amps),
>> not in proportions of the full range.  So if you measure thingsn in ADC
>> counts, then your noise and offset would certainly go up, and I would
>> expect your integral and differential nonlinearities to go up, too.
>>
>>> As for the interface between ADC and FPGA, if the ADC is running at 150
>>> MHz, at what clock frequency does the FIFO have to be (I believe it is
>>> going to be the same thing).
>>
>> If the ADC is _converting_ 150 Msps (mega samples/sec), then the FIFO
>> needs to be able to accept that.  For most FPGAs this means clocking the
>> FIFO logic with a minimum of 150MHz.
>>
>>> Can DSP blocks inside an FPGA be higher (or lower) than the input?  For
>>> instance if I create a 2x upsampling block, followed by a low-pass
> filter,
>>> then 2x decimation (I'm just making stuff up) can they run at different
>>> frequencies?
>>
>> Yes they can.  Running more than one clock domain in an FPGA means that
>> you have to pay careful attention to the signals that cross those clock
>> domains -- but it not only can be done, it is often done.
>>
>>> Does it makes sense for an FPGA run at its maximum frequency, higher
> than
>>> the ADC frequency?
>>
>> FPGAs don't really have "maximum frequencies".  They have a number of
>> different delays for various paths in the device (short paths generally
>> being faster than long ones, kind of).  So vendors sell them in "speed
>> grades", and what clock frequencies can be reliably attained with a
>> particular part is heavily dependent on the details of the design.
>>
>> Usually when an FPGA vendor advertises an FPGA speed it's because
>> they've benchmarked the thing with some application that is inherently a
>> good fit for the part, which lets them advertise the highest clock they
> can.
>>
>> It may indeed make sense for an FPGA to run at a higher frequency than
>> the ADC (and perhaps to run all the FPGA at a high frequency, to avoid
>> multiple clock domains).  But the higher you push the frequency of
>> operation, the harder it will be for the design to meet timing.
>> Consistently reaching timing closure with an aggressively fast FPGA
>> design is one of the things that separates the men from the boys when it
>> comes to FPGA design.
>>
 > Could you please explain to me exactly what FPGA experts mean by
 > timing or timing closure?
 >
 > Does it have to do with the fact that in reality there are delays as
 > signals pass through the logic circuits?

Yes.  "Timing closure" means that when all the delays in the circuit are 
added up, they come out to something less than the maximum allowable 
delay.  This allowable delay is usually your clock period, minus a bit 
for jitter.

Modern FPGA synthesis tools will try to put speed sensitive stuff close 
together, to speed up a particular path -- but they can only do so much, 
so the FPGA designer has to specify a circuit that has a chance of working.

 > Also, I do not understand how a dsp block processes data rates faster
 > than the input.  So say there is a 150 MHz input coming in and I
 > generate a low-pass filter that runs at 200 Mhz, I would think that
 > at the output at certain cycles there is nothing coming out since
 > there isn't enough data coming in.  Am I visualizing this correctly?

Your question was "Can DSP blocks inside an FPGA be higher (or lower) 
than the input?".  I took that to mean "Can DSP blocks inside an FPGA be 
_clocked at_ higher (or lower) _rates_ than the input?"

The answer to that question is yes -- you can parallelize your algorithm 
and clock the blocks slower, or you can serialize your algorithms and 
clock the blocks faster (for instance, if you're sampling at 50MHz you 
may be able to use one multiplier clocked at 200MHz four times for each 
input sample).

For that matter, even if the block is designed to be "straight through", 
with no sample rate change, it could still be clocked faster than the 
input clock.  You would just need to buffer data going into and out of 
the filter with FIFOs, and extract data from the filter at the same 
speed it goes in.

And of course, you could up-sample.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

On Wed, 23 Mar 2011 19:22:47 +0000, glen herrmannsfeldt wrote:

> pacman101 <janpac01@n_o_s_p_a_m.yahoo.com> wrote:
>  
>> I started studying ADC design and FPGA clocking and I have a lot of
>> questions.
>  
>> I would like to know if small signals that is in between the voltage
>> full-scale measurement range digitized with the same amount of
>> resolution? If it isn't so, is there a way such that the ADC is
>> designed so that no matter what the input amplitude is, the adc always
>> digitizes it at full (or near full to avoid saturation) resolution (ie
>> vary the reference voltage to the ADC)?
> 
> In the case of DVMs (Digital Volt Meters) this is called autoranging. It
> was rare for analog meters, but is common for digital meters.
> 
> It takes some time, and normally comes in discrete steps.
> 
> In audio systems, it is called AGC or ALC, Automatic (Gain or Level)
> Control.  In this case, unlike the DVM case, one is less concerned with
> absolute level, and more with the variation of the signal.
> 
> Consider those two, and compare to the problem you are working on.
> 
> -- glen

But it isn't a common function of A to D converters, if it's a function 
of any at all -- it's a function of the circuitry that precedes the ADC.

Autoranging, however, would be the way to go.

-- 
http://www.wescottdesign.com

Tim Wescott <tim@seemywebsite.com> wrote:
>> pacman101 <janpac01@n_o_s_p_a_m.yahoo.com> wrote:
  
>>> I started studying ADC design and FPGA clocking and I have a lot of
>>> questions.
  
(snip, then I wrote) 
>> In the case of DVMs (Digital Volt Meters) this is called autoranging.
>> It was rare for analog meters, but is common for digital meters.
(snip) 
>> In audio systems, it is called AGC or ALC, Automatic (Gain or Level)
>> Control.  In this case, unlike the DVM case, one is less concerned with
>> absolute level, and more with the variation of the signal.

(snip) 
> But it isn't a common function of A to D converters, if it's a function 
> of any at all -- it's a function of the circuitry that precedes the ADC.

Sounds right, but some people have different ideas for what ADC
and DAC mean.

The converter boxes for digital television are called Digital to
Analog converters, as they convert digital television signals
to analog televisions signals.  Likely they have a DAC integrated
circuit (or more) inside.  There are also DAC for audio use,
to connect to the digital output of a CD player (or other digital
audio source).  

Reading again, I would agree, but with a some generalization,
a little more of the associated circuitry could also count.

-- glen

In RF (since I mostly study RF), when somebody says Automatic gain control
(or leveling) does the algorithm control the gain of a Low-Noise Amplifier?
 If not, what type of Amplifier is it controlling?

>Tim Wescott <tim@seemywebsite.com> wrote:
>>> pacman101 <janpac01@n_o_s_p_a_m.yahoo.com> wrote:
>  
>>>> I started studying ADC design and FPGA clocking and I have a lot of
>>>> questions.
>  
>(snip, then I wrote) 
>>> In the case of DVMs (Digital Volt Meters) this is called autoranging.
>>> It was rare for analog meters, but is common for digital meters.
>(snip) 
>>> In audio systems, it is called AGC or ALC, Automatic (Gain or Level)
>>> Control.  In this case, unlike the DVM case, one is less concerned
with
>>> absolute level, and more with the variation of the signal.
>
>(snip) 
>> But it isn't a common function of A to D converters, if it's a function

>> of any at all -- it's a function of the circuitry that precedes the
ADC.
>
>Sounds right, but some people have different ideas for what ADC
>and DAC mean.
>
>The converter boxes for digital television are called Digital to
>Analog converters, as they convert digital television signals
>to analog televisions signals.  Likely they have a DAC integrated
>circuit (or more) inside.  There are also DAC for audio use,
>to connect to the digital output of a CD player (or other digital
>audio source).  
>
>Reading again, I would agree, but with a some generalization,
>a little more of the associated circuitry could also count.
>
>-- glen
>

On 03/24/2011 06:00 AM, pacman101 wrote:
(top posting fixed -- hint, hint)

>> Tim Wescott<tim@seemywebsite.com>  wrote:
>>>> pacman101<janpac01@n_o_s_p_a_m.yahoo.com>  wrote:
>>
>>>>> I started studying ADC design and FPGA clocking and I have a lot of
>>>>> questions.
>>
>> (snip, then I wrote)
>>>> In the case of DVMs (Digital Volt Meters) this is called autoranging.
>>>> It was rare for analog meters, but is common for digital meters.
>> (snip)
>>>> In audio systems, it is called AGC or ALC, Automatic (Gain or Level)
>>>> Control.  In this case, unlike the DVM case, one is less concerned
> with
>>>> absolute level, and more with the variation of the signal.
>>
>> (snip)
>>> But it isn't a common function of A to D converters, if it's a function
>
>>> of any at all -- it's a function of the circuitry that precedes the
> ADC.
>>
>> Sounds right, but some people have different ideas for what ADC
>> and DAC mean.
>>
>> The converter boxes for digital television are called Digital to
>> Analog converters, as they convert digital television signals
>> to analog televisions signals.  Likely they have a DAC integrated
>> circuit (or more) inside.  There are also DAC for audio use,
>> to connect to the digital output of a CD player (or other digital
>> audio source).
>>
>> Reading again, I would agree, but with a some generalization,
>> a little more of the associated circuitry could also count.
>>
>> -- glen
>>
 > In RF (since I mostly study RF), when somebody says Automatic gain
 > control (or leveling) does the algorithm control the gain of a
 > Low-Noise Amplifier?   If not, what type of Amplifier is it
 > controlling?

It is difficult to maintain noise figure and distortion resistance while 
gain controlling an amplifier.  So AGC is rarely applied in the front end.

In a superheterodyne receiver AGC generally controls the gain of an IF 
amplifier, or it controls one or more attenuators in the IF strip.

In a direct conversion receiver AGC generally controls the gain at baseband.

At any rate, if there's AGC it generally controls an amplifier that 
comes after any fixed bandlimiting filters.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

I see.  Is autoranging different from automatic gain control?

>On 03/24/2011 06:00 AM, pacman101 wrote:
>(top posting fixed -- hint, hint)
>
>>> Tim Wescott<tim@seemywebsite.com>  wrote:
>>>>> pacman101<janpac01@n_o_s_p_a_m.yahoo.com>  wrote:
>>>
>>>>>> I started studying ADC design and FPGA clocking and I have a lot of
>>>>>> questions.
>>>
>>> (snip, then I wrote)
>>>>> In the case of DVMs (Digital Volt Meters) this is called
autoranging.
>>>>> It was rare for analog meters, but is common for digital meters.
>>> (snip)
>>>>> In audio systems, it is called AGC or ALC, Automatic (Gain or Level)
>>>>> Control.  In this case, unlike the DVM case, one is less concerned
>> with
>>>>> absolute level, and more with the variation of the signal.
>>>
>>> (snip)
>>>> But it isn't a common function of A to D converters, if it's a
function
>>
>>>> of any at all -- it's a function of the circuitry that precedes the
>> ADC.
>>>
>>> Sounds right, but some people have different ideas for what ADC
>>> and DAC mean.
>>>
>>> The converter boxes for digital television are called Digital to
>>> Analog converters, as they convert digital television signals
>>> to analog televisions signals.  Likely they have a DAC integrated
>>> circuit (or more) inside.  There are also DAC for audio use,
>>> to connect to the digital output of a CD player (or other digital
>>> audio source).
>>>
>>> Reading again, I would agree, but with a some generalization,
>>> a little more of the associated circuitry could also count.
>>>
>>> -- glen
>>>
> > In RF (since I mostly study RF), when somebody says Automatic gain
> > control (or leveling) does the algorithm control the gain of a
> > Low-Noise Amplifier?   If not, what type of Amplifier is it
> > controlling?
>
>It is difficult to maintain noise figure and distortion resistance while 
>gain controlling an amplifier.  So AGC is rarely applied in the front
end.
>
>In a superheterodyne receiver AGC generally controls the gain of an IF 
>amplifier, or it controls one or more attenuators in the IF strip.
>
>In a direct conversion receiver AGC generally controls the gain at
baseband.
>
>At any rate, if there's AGC it generally controls an amplifier that 
>comes after any fixed bandlimiting filters.
>
>-- 
>
>Tim Wescott
>Wescott Design Services
>http://www.wescottdesign.com
>
>Do you need to implement control loops in software?
>"Applied Control Theory for Embedded Systems" was written for you.
>See details at http://www.wescottdesign.com/actfes/actfes.html
>