implementation of a very fast lookup table

Hi,

I need to implement a 16bit lookup-table that can run at 800MS/s. I
also need to update the table but at a much slower rate of about 1MHz.
I wonder if there is any solution that fits these specs.
Any pointer is greatly appreciated.

Alireza <dastgheib@gmail.com> wrote:
 
> I need to implement a 16bit lookup-table that can run at 800MS/s. I
> also need to update the table but at a much slower rate of about 1MHz.
> I wonder if there is any solution that fits these specs.
> Any pointer is greatly appreciated.

You gave the rate, but not the latency.

The usual solution is multiple tables in parallel, but you have
to be able to live with the latency.

Dual-port RAM will allow for writes without delaying the read.

(The block-RAM in the currently popular FPGAs is synchronous.
Assuming proper clock domain logic, you either get the old or
new value on read.)

800MHz sounds a little fast, but 200MHz is slow, and four are
easy to find.  (18x18 is the usual size for FPGAs.)

-- glen

glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:

(snip, I wrote)

> (The block-RAM in the currently popular FPGAs is synchronous.
> Assuming proper clock domain logic, you either get the old or
> new value on read.)

> 800MHz sounds a little fast, but 200MHz is slow, and four are
> easy to find.  (18x18 is the usual size for FPGAs.)

Oops, that isn't what I meant.

The configurations allowed for the Spartan 3 family are:

36x512, 18x1024, 9x2048, 4x4096, 2x8192, or 1x16384.

The FPGAs in the Spartan 3 family have between 4 and 104
such RAM blocks.

Virtex is faster, but more expensive.

-- glen

On Jun 10, 1:11&#4294967295;pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
>
> (snip, I wrote)
>
> > (The block-RAM in the currently popular FPGAs is synchronous.
> > Assuming proper clock domain logic, you either get the old or
> > new value on read.)
> > 800MHz sounds a little fast, but 200MHz is slow, and four are
> > easy to find. &#4294967295;(18x18 is the usual size for FPGAs.)
>
> Oops, that isn't what I meant.
>
> The configurations allowed for the Spartan 3 family are:
>
> 36x512, 18x1024, 9x2048, 4x4096, 2x8192, or 1x16384.
>
> The FPGAs in the Spartan 3 family have between 4 and 104
> such RAM blocks.
>
> Virtex is faster, but more expensive.
>
> -- glen

Thanks, Glen. Latency is not important in this application and what
you're suggesting sounds pretty good.
I am working with system generator. I assume it will allow me to split
my design into a few Spartan devices or one Virtex and a few Spartans.

Thanks,
Alireza

How large is your design that it won't fit in a single FPGA?  They come in some pretty huge sizes these days. 

Rick

On Jun 10, 4:06&#4294967295;pm, rickman <gnu...@gmail.com> wrote:
> How large is your design that it won't fit in a single FPGA? &#4294967295;They come in some pretty huge sizes these days.
>
> Rick

I need a LUT that can work at 800MS/s. Glen suggested that I
interleave a few FPGAs to get to that speed. That's why I will need
multiple FPGAs.

Alireza

rickman <gnuarm@gmail.com> wrote:

> How large is your design that it won't fit in a single FPGA?  

I had a design (which I didn't convince anyone to fund) that fit
in 2000 of the biggest Spartan3E.  It does 5e19 six-bit add/subtract
operations per day, or about 5e14 per second.

> They come in some pretty huge sizes these days. 

Yes, but the larger ones are much more expensive, per logic
unit, than some of the smaller ones.  

-- glen

Alireza <dastgheib@gmail.com> wrote:

> On Jun 10, 4:06&#4294967295;pm, rickman <gnu...@gmail.com> wrote:
>> How large is your design that it won't fit in a single FPGA? &#4294967295;
>> They come in some pretty huge sizes these days.
 
> I need a LUT that can work at 800MS/s. Glen suggested that I
> interleave a few FPGAs to get to that speed. That's why I will need
> multiple FPGAs.

Well, the suggestion was to interleave the RAM access.  That could
be done with multiple RAMs in one FPGA.  Without knowing the
width and depth, it is hard to say.

Virtex is much faster, and much more expensive, than Spartan.

-- glen

I need to say this and please don't take offense, if you are making such a fundamental error as this, it is pretty clear that you don't know enough about FPGAs to complete any practical project, much less one that will require the design to work at 800 MSPS.  I don't mean to be rude, but have you considered hiring a consultant?  Even if it is just someone to show you how to do the project which you then do yourself, it might be wise to keep someone knowledgeable in the loop to sanity check your design until it is done.  

If you are interested, I am available.  You can contact me through the email address on my web page arius.com. 

Rick

Sorry, I am still not sure I should do this. 
1. Is it possible to input different clock signals to a single FPGA and have different RAMs use different clocks?
2. Even if I interleave a few low speed RAMs I still need a switch at the end that runs at the full speed and loops through the RAMs. Do you know how I can implement that switch?

Alireza