Is 3rd-order PLL capable to track large freq offset

Hi, all

I wrote a small simulation program to evaluate phase tracking performance
for 2nd-order digital PLL and 3rd-order digital PLL. Noise bandwidth of
2nd-order loop and 3rd-order loop are 60Hz and 54Hz, respectively.
Simulation results indicate that:

1. 2nd-order loop can track large frequency offset, 340Hz for example. The
larger frequency offset, the longer time it takes to track the phase. But
2nd-order loop cannot track large frequency ramp, 2KHz/s for example.

2. 3rd-order loop tracks 2KHz/s frequency ramp easily without phase error.
But it cannot track 340Hz frequency offset! When tracking frequency offset,
the output of 1st stage integrator in loop filter should approach zero
after some time, and output of 2nd stage integrator in loop filter should
not change correspondingly. But from simulation result, I saw 1st stage
integrator output became less and less continuously. As a result, 2nd stage
integrator output decreased with faster rate and finally overflew.

My question is that is 3rd-order loop has limit ability to track frequency
offset?

Regrads,
Mi

On 06/11/2011 06:17 AM, mccatec wrote:
> Hi, all
>
> I wrote a small simulation program to evaluate phase tracking performance
> for 2nd-order digital PLL and 3rd-order digital PLL. Noise bandwidth of
> 2nd-order loop and 3rd-order loop are 60Hz and 54Hz, respectively.
> Simulation results indicate that:
>
> 1. 2nd-order loop can track large frequency offset, 340Hz for example. The
> larger frequency offset, the longer time it takes to track the phase. But
> 2nd-order loop cannot track large frequency ramp, 2KHz/s for example.

I believe that when you say "track large frequency offset" you mean that 
you are starting the loop with an offset, and looking for it to lock -- 
tracking is what happens _after_ locking.

> 2. 3rd-order loop tracks 2KHz/s frequency ramp easily without phase error.
> But it cannot track 340Hz frequency offset! When tracking frequency offset,
> the output of 1st stage integrator in loop filter should approach zero
> after some time, and output of 2nd stage integrator in loop filter should
> not change correspondingly. But from simulation result, I saw 1st stage
> integrator output became less and less continuously. As a result, 2nd stage
> integrator output decreased with faster rate and finally overflew.
>
> My question is that is 3rd-order loop has limit ability to track frequency
> offset?

I assume you mean a loop that has two integrators in the loop filter, 
vs. one -- in which case you mean "type two" (one integrator in the 
controller, with the NCO forming the other one), and "type three".

If so, then the extra integrator in the loop filter -- particularly if 
it is allowed to take on large random values -- will make lock more 
difficult.  If at all possible, you want to have a startup mode, where 
you disable the frequency ramp integrator, and possibly modify the gains 
in your loop filter.  Then, once you detect that the loop is locked 
(which is not always trivial in a noisy environment) you set the loop 
gains to their 'run' values, or perhaps let the loop gains evolve into 
their 'run' values if doing so suddenly might throw the loop out of lock.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

Thx for your reply. So it is reasonable for a type III 3rd-order PLL being
hard to lock-in from a large initial frequency offset, possibly caused by
poor acquisition, right? By 'start-up mode' I guess you mean loop switch
between FLL and PLL or type II PLL and type III PLL, or combining FLL and
PLL together like Kaplan said in his book 'Understanding GPS: Principles
and Applications'. Currently I use type III PLL directly after acquisition.
Maybe it's safer to use a 'start-up mode', I will try.

>On 06/11/2011 06:17 AM, mccatec wrote:
>> Hi, all
>>
>> I wrote a small simulation program to evaluate phase tracking
performance
>> for 2nd-order digital PLL and 3rd-order digital PLL. Noise bandwidth of
>> 2nd-order loop and 3rd-order loop are 60Hz and 54Hz, respectively.
>> Simulation results indicate that:
>>
>> 1. 2nd-order loop can track large frequency offset, 340Hz for example.
The
>> larger frequency offset, the longer time it takes to track the phase.
But
>> 2nd-order loop cannot track large frequency ramp, 2KHz/s for example.
>
>I believe that when you say "track large frequency offset" you mean that 
>you are starting the loop with an offset, and looking for it to lock -- 
>tracking is what happens _after_ locking.
>
>> 2. 3rd-order loop tracks 2KHz/s frequency ramp easily without phase
error.
>> But it cannot track 340Hz frequency offset! When tracking frequency
offset,
>> the output of 1st stage integrator in loop filter should approach zero
>> after some time, and output of 2nd stage integrator in loop filter
should
>> not change correspondingly. But from simulation result, I saw 1st stage
>> integrator output became less and less continuously. As a result, 2nd
stage
>> integrator output decreased with faster rate and finally overflew.
>>
>> My question is that is 3rd-order loop has limit ability to track
frequency
>> offset?
>
>I assume you mean a loop that has two integrators in the loop filter, 
>vs. one -- in which case you mean "type two" (one integrator in the 
>controller, with the NCO forming the other one), and "type three".
>
>If so, then the extra integrator in the loop filter -- particularly if 
>it is allowed to take on large random values -- will make lock more 
>difficult.  If at all possible, you want to have a startup mode, where 
>you disable the frequency ramp integrator, and possibly modify the gains 
>in your loop filter.  Then, once you detect that the loop is locked 
>(which is not always trivial in a noisy environment) you set the loop 
>gains to their 'run' values, or perhaps let the loop gains evolve into 
>their 'run' values if doing so suddenly might throw the loop out of lock.
>
>-- 
>
>Tim Wescott
>Wescott Design Services
>http://www.wescottdesign.com
>
>Do you need to implement control loops in software?
>"Applied Control Theory for Embedded Systems" was written for you.
>See details at http://www.wescottdesign.com/actfes/actfes.html
>

On Jun 12, 1:17&#4294967295;am, "mccatec" <mccatec@n_o_s_p_a_m.googlemail.com>
wrote:
> Hi, all
>
> I wrote a small simulation program to evaluate phase tracking performance
> for 2nd-order digital PLL and 3rd-order digital PLL. Noise bandwidth of
> 2nd-order loop and 3rd-order loop are 60Hz and 54Hz, respectively.
> Simulation results indicate that:
>
> 1. 2nd-order loop can track large frequency offset, 340Hz for example. The
> larger frequency offset, the longer time it takes to track the phase. But
> 2nd-order loop cannot track large frequency ramp, 2KHz/s for example.
>
> 2. 3rd-order loop tracks 2KHz/s frequency ramp easily without phase error.
> But it cannot track 340Hz frequency offset! When tracking frequency offset,
> the output of 1st stage integrator in loop filter should approach zero
> after some time, and output of 2nd stage integrator in loop filter should
> not change correspondingly. But from simulation result, I saw 1st stage
> integrator output became less and less continuously. As a result, 2nd stage
> integrator output decreased with faster rate and finally overflew.
>
> My question is that is 3rd-order loop has limit ability to track frequency
> offset?
>
> Regrads,
> Mi

Do you mean a loop with two integrators + the VCO? Good tracking comes
about by high gain at the frequencies of interest.
nothing more. of course you must maintain stability with a good phase
margin and this becomes harder as the type (no of integrators) go up.
You must trade off bandwidth for phase margin.

F

On 06/11/2011 10:07 AM, mccatec wrote:
(top post fixed)
>
>> On 06/11/2011 06:17 AM, mccatec wrote:
>>> Hi, all
>>>
>>> I wrote a small simulation program to evaluate phase tracking
> performance
>>> for 2nd-order digital PLL and 3rd-order digital PLL. Noise bandwidth of
>>> 2nd-order loop and 3rd-order loop are 60Hz and 54Hz, respectively.
>>> Simulation results indicate that:
>>>
>>> 1. 2nd-order loop can track large frequency offset, 340Hz for example.
> The
>>> larger frequency offset, the longer time it takes to track the phase.
> But
>>> 2nd-order loop cannot track large frequency ramp, 2KHz/s for example.
>>
>> I believe that when you say "track large frequency offset" you mean that
>> you are starting the loop with an offset, and looking for it to lock --
>> tracking is what happens _after_ locking.
>>
>>> 2. 3rd-order loop tracks 2KHz/s frequency ramp easily without phase
> error.
>>> But it cannot track 340Hz frequency offset! When tracking frequency
> offset,
>>> the output of 1st stage integrator in loop filter should approach zero
>>> after some time, and output of 2nd stage integrator in loop filter
> should
>>> not change correspondingly. But from simulation result, I saw 1st stage
>>> integrator output became less and less continuously. As a result, 2nd
> stage
>>> integrator output decreased with faster rate and finally overflew.
>>>
>>> My question is that is 3rd-order loop has limit ability to track
> frequency
>>> offset?
>>
>> I assume you mean a loop that has two integrators in the loop filter,
>> vs. one -- in which case you mean "type two" (one integrator in the
>> controller, with the NCO forming the other one), and "type three".
>>
>> If so, then the extra integrator in the loop filter -- particularly if
>> it is allowed to take on large random values -- will make lock more
>> difficult.  If at all possible, you want to have a startup mode, where
>> you disable the frequency ramp integrator, and possibly modify the gains
>> in your loop filter.  Then, once you detect that the loop is locked
>> (which is not always trivial in a noisy environment) you set the loop
>> gains to their 'run' values, or perhaps let the loop gains evolve into
>> their 'run' values if doing so suddenly might throw the loop out of lock.
>>
>> --
>>
>> Tim Wescott
>> Wescott Design Services
>> http://www.wescottdesign.com
>>
>> Do you need to implement control loops in software?
>> "Applied Control Theory for Embedded Systems" was written for you.
>> See details at http://www.wescottdesign.com/actfes/actfes.html
>>
 > Thx for your reply. So it is reasonable for a type III 3rd-order PLL 
being
 > hard to lock-in from a large initial frequency offset, possibly caused by
 > poor acquisition, right?

Yup.

 > By 'start-up mode' I guess you mean loop switch
 > between FLL and PLL or type II PLL and type III PLL,

Yup.

 > or combining FLL and
 > PLL together like Kaplan said in his book 'Understanding GPS: Principles
 > and Applications'.

I'm not familiar with that book, but if he's got a solution that lets 
you combine the two solutions, it may be worth a look.

 > Currently I use type III PLL directly after acquisition.
 > Maybe it's safer to use a 'start-up mode', I will try.

PLL's can be tricky.  Normally I detest control loops that switch modes 
(they always seem to end up in the wrong modes at the worst possible 
times, and need more effort on the mode switching than you think).  But 
I often use it on PLL's, because it often seems to be necessary in spite 
of my prejudice.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html