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Reducing slew rate - for TI DSP

Started by gutta July 26, 2011
Hi,

i am using TI-C6452 DSP of 720MHz. The DSP has the peripherals FPGA ,DDR2.
I want to reduce the slew rate or driver strength to control the GPIO I/O,
especially for EMIF.Do some one know any bit corresponding to slew rate or
driver strength in any of the specs of the TI DSP? or is there any method
to do it?

 

Regards,
Ramana.


On Tue, 26 Jul 2011 09:15:58 -0500, gutta wrote:

> Hi, > > i am using TI-C6452 DSP of 720MHz. The DSP has the peripherals FPGA > ,DDR2. I want to reduce the slew rate or driver strength to control the > GPIO I/O, especially for EMIF.Do some one know any bit corresponding to > slew rate or driver strength in any of the specs of the TI DSP? or is > there any method to do it?
If there's a setup for slew rate then it'll be in the GPIO setup, so read that section of the documentation. It may be called a drive current -- reducing the drive current will reduce the slew. Putting a series resistor at the processor pin should reduce EMI and well as reducing reflections. Check to see if TI has posted a white paper about EMI and that series of chips. -- www.wescottdesign.com
On Tue, 26 Jul 2011 09:15:58 -0500, gutta wrote:

> Hi, > > i am using TI-C6452 DSP of 720MHz. The DSP has the peripherals FPGA > ,DDR2. I want to reduce the slew rate or driver strength to control the > GPIO I/O, especially for EMIF.Do some one know any bit corresponding to > slew rate or driver strength in any of the specs of the TI DSP? or is > there any method to do it?
I read this before and didn't see the conflict: Surely you _either_ want to reduce slew rate and _increase_ the driver strength, or _increase_ slew rate and _decrease_ the driver strength. Decreasing both slew rate and driver strength is an inherent chip issue, or a board issue. -- www.wescottdesign.com
On Jul 26, 6:11=A0pm, Tim Wescott <t...@seemywebsite.com> wrote:
> On Tue, 26 Jul 2011 09:15:58 -0500, gutta wrote: > > Hi, > > > i am using TI-C6452 DSP of 720MHz. The DSP has the peripherals FPGA > > ,DDR2. I want to reduce the slew rate or driver strength to control the > > GPIO I/O, especially for EMIF.Do some one know any bit corresponding to > > slew rate or driver strength in any of the specs of the TI DSP? or is > > there any method to do it? > > I read this before and didn't see the conflict: > > Surely you _either_ want to reduce slew rate and _increase_ the driver > strength, or _increase_ slew rate and _decrease_ the driver strength. =A0 > Decreasing both slew rate and driver strength is an inherent chip issue, > or a board issue.
I don't think so. Reducing the strength of the driver will reduce the rate at which it can slew. Were you thinking of slew time, as I did when I first read the OP's post? The series resistor seems like a good suggestion. With the circuit capacitances, it might not take much resistance. Of course, an analog low-pass filter may not be hi-tech enough to please. :-) Jerry -- Engineering is the art of making what you want from things you can get.
On Tue, 26 Jul 2011 15:19:09 -0700, Jerry Avins wrote:

> On Jul 26, 6:11&nbsp;pm, Tim Wescott <t...@seemywebsite.com> wrote: >> On Tue, 26 Jul 2011 09:15:58 -0500, gutta wrote: >> > Hi, >> >> > i am using TI-C6452 DSP of 720MHz. The DSP has the peripherals FPGA >> > ,DDR2. I want to reduce the slew rate or driver strength to control >> > the GPIO I/O, especially for EMIF.Do some one know any bit >> > corresponding to slew rate or driver strength in any of the specs of >> > the TI DSP? or is there any method to do it? >> >> I read this before and didn't see the conflict: >> >> Surely you _either_ want to reduce slew rate and _increase_ the driver >> strength, or _increase_ slew rate and _decrease_ the driver strength. >> Decreasing both slew rate and driver strength is an inherent chip >> issue, or a board issue. > > I don't think so. Reducing the strength of the driver will reduce the > rate at which it can slew. Were you thinking of slew time, as I did when > I first read the OP's post? The series resistor seems like a good > suggestion. With the circuit capacitances, it might not take much > resistance. Of course, an analog low-pass filter may not be hi-tech > enough to please. :-)
And to think -- I'm working for pay today. Series resistances on digital outputs is a pretty common way to condition high-speed lines in digital circuits. So much so, that some manufacturers started controlling the impedance on the output drivers of their chips. It's very handy when you have a 300 pin FPGA not to need a sea of 0402 resistors that takes almost as much board space as the active part they're supporting. -- www.wescottdesign.com
On Jul 26, 5:19&#2013266080;pm, Jerry Avins <j...@ieee.org> wrote:
> On Jul 26, 6:11&#2013266080;pm, Tim Wescott <t...@seemywebsite.com> wrote: > > > On Tue, 26 Jul 2011 09:15:58 -0500, gutta wrote: > > > Hi, > > > > i am using TI-C6452 DSP of 720MHz. The DSP has the peripherals FPGA > > > ,DDR2. I want to reduce the slew rate or driver strength to control the > > > GPIO I/O, especially for EMIF.Do some one know any bit corresponding to > > > slew rate or driver strength in any of the specs of the TI DSP? or is > > > there any method to do it? > > > I read this before and didn't see the conflict: > > > Surely you _either_ want to reduce slew rate and _increase_ the driver > > strength, or _increase_ slew rate and _decrease_ the driver strength. &#2013266080; > > Decreasing both slew rate and driver strength is an inherent chip issue, > > or a board issue. > > I don't think so. Reducing the strength of the driver will reduce the > rate at which it can slew. Were you thinking of slew time, as I did > when I first read the OP's post? The series resistor seems like a good > suggestion. With the circuit capacitances, it might not take much > resistance. Of course, an analog low-pass filter may not be hi-tech > enough to please. :-) > > Jerry > -- > Engineering is the art of making what you want from things you can get.
Remember that a signal can't radiate (EMI) unless current flows. Standing waves don't radiate. In the *old* days we put in series resistors to reduce the ringing and noise during switching that was causing unwanted logic transistions as the ringing passed through the level threshholds (we called irt making the signal look good). Maurice

gutta wrote:

> Hi, > > i am using TI-C6452 DSP of 720MHz. The DSP has the peripherals FPGA ,DDR2. > I want to reduce the slew rate or driver strength to control the GPIO I/O, > especially for EMIF.Do some one know any bit corresponding to slew rate or > driver strength in any of the specs of the TI DSP? or is there any method > to do it?
AFAIR the EMIF of TI does not have the adjustable driver strength feature. Not many of the MCUs have that. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com