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Fractional Resampling WCDMA gives noise

Started by DSPWirelessGuy July 29, 2011

Hi  Steve,

Thanks for your inputs.

I had one more question


If I use data at 4x or 8x before downsampling, I may have better chance
of hitting the correcting sampling point and reduce jitter to acceptable
level.
Or adjust the DAC sampling at integer U/D sampling at higher rate. 

Is this understanding correct?

Regards
Huzaifa
>>Hi Steve, >> >>Yeah, I actually meant Jitter. Is there any way of reducing this jitter. >>I also tried to use interpolation by estimating Early ontime late >>mechanism. But no use. I have only tried linear interpolation so far. >> >>Although resampling pattern seems horrible, it is not as bad. I get
Mean
>>Squared Error of about 7dB.This is still not good enough for higher >>modulation. >> >>Seems I will have to use polyphase mechanism to resample. >> >>Thanks >>Huzaifa > >As I said before, your 7dB figure is an average over the 25 sample >sequence. With your pattern, you build up 7/8ths of a sample of timing >error, and release it in one go. If you look at the 8 RMS errors
calculated
>from the 8 phases of your sequence you will see very different errors >across those phases. > >Steve > >
Generally, yes, if you don't mind some significant residual error rate
due to the jitter you can upsample to 4-8x (or higher) and just pick
the sample that is closest to the eye opening, depending on the
rolloff rate (i.e., excess bandwidth) of the RRC filter.

You can look at Figure 7 here and get an idea of how the pulse shape
affects the sensitivity to jitter:

http://www.dsprelated.com/showarticle/60.php

Interpolating every sample and picking the best, however you decide
how to pick the best one, is also fairly inefficient computationally
since you wind up computing a bunch of samples that you don't need or
use.

The main avantages of using a polyphase or Farrow structure in the
demodulator is that you compute only the samples that you're going to
use and you can interpolate exactly where you want, i.e., where you
think the zero-ISI point is.


On Mon, 01 Aug 2011 03:50:17 -0500, "Huzaifa Kapasi"
<huzaifa.kapasi@n_o_s_p_a_m.tcs.com> wrote:

> > >Hi Steve, > >Thanks for your inputs. > >I had one more question > > >If I use data at 4x or 8x before downsampling, I may have better chance >of hitting the correcting sampling point and reduce jitter to acceptable >level. >Or adjust the DAC sampling at integer U/D sampling at higher rate. > >Is this understanding correct? > >Regards >Huzaifa >>>Hi Steve, >>> >>>Yeah, I actually meant Jitter. Is there any way of reducing this jitter. >>>I also tried to use interpolation by estimating Early ontime late >>>mechanism. But no use. I have only tried linear interpolation so far. >>> >>>Although resampling pattern seems horrible, it is not as bad. I get >Mean >>>Squared Error of about 7dB.This is still not good enough for higher >>>modulation. >>> >>>Seems I will have to use polyphase mechanism to resample. >>> >>>Thanks >>>Huzaifa >> >>As I said before, your 7dB figure is an average over the 25 sample >>sequence. With your pattern, you build up 7/8ths of a sample of timing >>error, and release it in one go. If you look at the 8 RMS errors >calculated >>from the 8 phases of your sequence you will see very different errors >>across those phases. >> >>Steve >> >>
Eric Jacobsen http://www.ericjacobsen.org http://www.dsprelated.com/blogs-1//Eric_Jacobsen.php
Hi Eric

Thanks for your reply. I visited your articles on jitter. It was very
helpful.

Regarding the problem I had, I managed to have some architectural changes
and get the sampling frequency as integer multiple. I thought this was
relatively the only best solution that could be worked out at the moment.
Now the onus is on the accuracy and stability of my ADC.


Regards
Huzaifa


>Generally, yes, if you don't mind some significant residual error rate >due to the jitter you can upsample to 4-8x (or higher) and just pick >the sample that is closest to the eye opening, depending on the >rolloff rate (i.e., excess bandwidth) of the RRC filter. > >You can look at Figure 7 here and get an idea of how the pulse shape >affects the sensitivity to jitter: > >http://www.dsprelated.com/showarticle/60.php > >Interpolating every sample and picking the best, however you decide >how to pick the best one, is also fairly inefficient computationally >since you wind up computing a bunch of samples that you don't need or >use. > >The main avantages of using a polyphase or Farrow structure in the >demodulator is that you compute only the samples that you're going to >use and you can interpolate exactly where you want, i.e., where you >think the zero-ISI point is. > > >On Mon, 01 Aug 2011 03:50:17 -0500, "Huzaifa Kapasi" ><huzaifa.kapasi@n_o_s_p_a_m.tcs.com> wrote: > >> >> >>Hi Steve, >> >>Thanks for your inputs. >> >>I had one more question >> >> >>If I use data at 4x or 8x before downsampling, I may have better chance >>of hitting the correcting sampling point and reduce jitter to acceptable >>level. >>Or adjust the DAC sampling at integer U/D sampling at higher rate. >> >>Is this understanding correct? >> >>Regards >>Huzaifa >>>>Hi Steve, >>>> >>>>Yeah, I actually meant Jitter. Is there any way of reducing this
jitter.
>>>>I also tried to use interpolation by estimating Early ontime late >>>>mechanism. But no use. I have only tried linear interpolation so far. >>>> >>>>Although resampling pattern seems horrible, it is not as bad. I get >>Mean >>>>Squared Error of about 7dB.This is still not good enough for higher >>>>modulation. >>>> >>>>Seems I will have to use polyphase mechanism to resample. >>>> >>>>Thanks >>>>Huzaifa >>> >>>As I said before, your 7dB figure is an average over the 25 sample >>>sequence. With your pattern, you build up 7/8ths of a sample of timing >>>error, and release it in one go. If you look at the 8 RMS errors >>calculated >>>from the 8 phases of your sequence you will see very different errors >>>across those phases. >>> >>>Steve >>> >>> > >Eric Jacobsen >http://www.ericjacobsen.org >http://www.dsprelated.com/blogs-1//Eric_Jacobsen.php >
Just add a clarification. I dont have any channel at the moment. All I need
to is resample the received data at correct timing instant.However, farrow
structure, as you suggested, would be a better option otherwise.

Regards
Huzaifa

>Hi Eric > >Thanks for your reply. I visited your articles on jitter. It was very >helpful. > >Regarding the problem I had, I managed to have some architectural changes >and get the sampling frequency as integer multiple. I thought this was >relatively the only best solution that could be worked out at the moment. >Now the onus is on the accuracy and stability of my ADC. > > >Regards >Huzaifa > > >>Generally, yes, if you don't mind some significant residual error rate >>due to the jitter you can upsample to 4-8x (or higher) and just pick >>the sample that is closest to the eye opening, depending on the >>rolloff rate (i.e., excess bandwidth) of the RRC filter. >> >>You can look at Figure 7 here and get an idea of how the pulse shape >>affects the sensitivity to jitter: >> >>http://www.dsprelated.com/showarticle/60.php >> >>Interpolating every sample and picking the best, however you decide >>how to pick the best one, is also fairly inefficient computationally >>since you wind up computing a bunch of samples that you don't need or >>use. >> >>The main avantages of using a polyphase or Farrow structure in the >>demodulator is that you compute only the samples that you're going to >>use and you can interpolate exactly where you want, i.e., where you >>think the zero-ISI point is. >> >> >>On Mon, 01 Aug 2011 03:50:17 -0500, "Huzaifa Kapasi" >><huzaifa.kapasi@n_o_s_p_a_m.tcs.com> wrote: >> >>> >>> >>>Hi Steve, >>> >>>Thanks for your inputs. >>> >>>I had one more question >>> >>> >>>If I use data at 4x or 8x before downsampling, I may have better chance >>>of hitting the correcting sampling point and reduce jitter to
acceptable
>>>level. >>>Or adjust the DAC sampling at integer U/D sampling at higher rate. >>> >>>Is this understanding correct? >>> >>>Regards >>>Huzaifa >>>>>Hi Steve, >>>>> >>>>>Yeah, I actually meant Jitter. Is there any way of reducing this >jitter. >>>>>I also tried to use interpolation by estimating Early ontime late >>>>>mechanism. But no use. I have only tried linear interpolation so far. >>>>> >>>>>Although resampling pattern seems horrible, it is not as bad. I get >>>Mean >>>>>Squared Error of about 7dB.This is still not good enough for higher >>>>>modulation. >>>>> >>>>>Seems I will have to use polyphase mechanism to resample. >>>>> >>>>>Thanks >>>>>Huzaifa >>>> >>>>As I said before, your 7dB figure is an average over the 25 sample >>>>sequence. With your pattern, you build up 7/8ths of a sample of timing >>>>error, and release it in one go. If you look at the 8 RMS errors >>>calculated >>>>from the 8 phases of your sequence you will see very different errors >>>>across those phases. >>>> >>>>Steve >>>> >>>> >> >>Eric Jacobsen >>http://www.ericjacobsen.org >>http://www.dsprelated.com/blogs-1//Eric_Jacobsen.php >> >

Small clarification. There is no channel at the  moment and is not
expected. However, farrow structure as you suggest, would be a better
choice to address the issue.

Regards
Huzaifa



>Hi Eric > >Thanks for your reply. I visited your articles on jitter. It was very >helpful. > >Regarding the problem I had, I managed to have some architectural changes >and get the sampling frequency as integer multiple. I thought this was >relatively the only best solution that could be worked out at the moment. >Now the onus is on the accuracy and stability of my ADC. > > >Regards >Huzaifa > > >>Generally, yes, if you don't mind some significant residual error rate >>due to the jitter you can upsample to 4-8x (or higher) and just pick >>the sample that is closest to the eye opening, depending on the >>rolloff rate (i.e., excess bandwidth) of the RRC filter. >> >>You can look at Figure 7 here and get an idea of how the pulse shape >>affects the sensitivity to jitter: >> >>http://www.dsprelated.com/showarticle/60.php >> >>Interpolating every sample and picking the best, however you decide >>how to pick the best one, is also fairly inefficient computationally >>since you wind up computing a bunch of samples that you don't need or >>use. >> >>The main avantages of using a polyphase or Farrow structure in the >>demodulator is that you compute only the samples that you're going to >>use and you can interpolate exactly where you want, i.e., where you >>think the zero-ISI point is. >> >> >>On Mon, 01 Aug 2011 03:50:17 -0500, "Huzaifa Kapasi" >><huzaifa.kapasi@n_o_s_p_a_m.tcs.com> wrote: >> >>> >>> >>>Hi Steve, >>> >>>Thanks for your inputs. >>> >>>I had one more question >>> >>> >>>If I use data at 4x or 8x before downsampling, I may have better chance >>>of hitting the correcting sampling point and reduce jitter to
acceptable
>>>level. >>>Or adjust the DAC sampling at integer U/D sampling at higher rate. >>> >>>Is this understanding correct? >>> >>>Regards >>>Huzaifa >>>>>Hi Steve, >>>>> >>>>>Yeah, I actually meant Jitter. Is there any way of reducing this >jitter. >>>>>I also tried to use interpolation by estimating Early ontime late >>>>>mechanism. But no use. I have only tried linear interpolation so far. >>>>> >>>>>Although resampling pattern seems horrible, it is not as bad. I get >>>Mean >>>>>Squared Error of about 7dB.This is still not good enough for higher >>>>>modulation. >>>>> >>>>>Seems I will have to use polyphase mechanism to resample. >>>>> >>>>>Thanks >>>>>Huzaifa >>>> >>>>As I said before, your 7dB figure is an average over the 25 sample >>>>sequence. With your pattern, you build up 7/8ths of a sample of timing >>>>error, and release it in one go. If you look at the 8 RMS errors >>>calculated >>>>from the 8 phases of your sequence you will see very different errors >>>>across those phases. >>>> >>>>Steve >>>> >>>> >> >>Eric Jacobsen >>http://www.ericjacobsen.org >>http://www.dsprelated.com/blogs-1//Eric_Jacobsen.php >> >
Hi,

What comse to mind is (for example)
- polyphase 2/5 from 12 Msps to 4.8 Msps, maybe 14 taps as starting point
- polyphase 8/5 to 7.68 Msps
- RRC filter decimates by 2 to 3.84 Msps

The RRC filter running at the lower rate should save some resources,
compared to your original design.