# FFT scaling for hardware implementation

Started by September 30, 2011
Hi forum,

Do we really need to scale FFT for hardware implementation?

Up to now I found 2 situations where scaling has advantage:

1. It will save the logic because the internal word length remains
unchanged.
2. The twiddle factor multiplication error will be less.

The scaling also can be required if the output word length must be equal to
the input word length. In this case I have a 2 choices:

1. Do not scale (increase word length after each stage) and at the end
shift the result right by the corresponding value.
2. Use scaling.

How to make the choice if I don't care about gate counts?
Does the scaling significantly decrease the FFT error?

Thank you very much,
Tiksan.

On Sep 30, 10:03&#2013266080;am, "Syswip" <syswip@n_o_s_p_a_m.gmail.com> wrote:
> Hi forum, > > Do we really need to scale FFT for hardware implementation? > > Up to now I found 2 situations where scaling has advantage: > > 1. It will save the logic because the internal word length remains > unchanged. > 2. The twiddle factor multiplication error will be less. > > The scaling also can be required if the output word length must be equal to > the input word length. In this case I have a 2 choices: > > 1. Do not scale (increase word length after each stage) and at the end > shift the result right by the corresponding value. > 2. Use scaling. > > How to make the choice if I don't care about gate counts? > Does the scaling significantly decrease the FFT error? > > Thank you very much, > Tiksan.
Well, if you have a nearly fullscale sinusoid centered on one of your bin frequencies, the FFT's output will be (N/2) times your full scale in amplitude where N is the number of samples. Is this a problem to you? More than likely your encountered signals may not be such a pure sinusoid, but if your signal is not flat frequency wise, then you will likely need scaling somewhere in the process so as to not saturate or underflow. You should be able to find many articles on FFT scaling. Clay
Syswip <syswip@n_o_s_p_a_m.gmail.com> wrote:

>Do we really need to scale FFT for hardware implementation?
>[snip]
>1. Do not scale (increase word length after each stage) and at the end >shift the result right by the corresponding value.
>How to make the choice if I don't care about gate counts?
If you don't care about gate counts, or clock speed, then it doesn't matter. However you might think about just how large some of these word widths are before concluding you don't care about gate counts. How many gates is a 384 x 16 bit multiplier? How slow is it? Steve
>Syswip <syswip@n_o_s_p_a_m.gmail.com> wrote: > >>Do we really need to scale FFT for hardware implementation? > >>[snip] > >>1. Do not scale (increase word length after each stage) and at the end >>shift the result right by the corresponding value. > >>How to make the choice if I don't care about gate counts? > >If you don't care about gate counts, or clock speed, then it doesn't >matter. However you might think about just how large some of these >word widths are before concluding you don't care about gate counts. >How many gates is a 384 x 16 bit multiplier? How slow is it? > > >Steve >
Thanks Steve, What about error propagation? Does the scaling decrease FFT rounding error propagation? Bests, Tiksan.
Syswip <syswip@n_o_s_p_a_m.gmail.com> wrote:
>Do we really need to scale FFT for hardware implementation? >[snip]