When a DPLL is used specifically for symbol timing sync (early-late method), how does one determine if it is locked? Since in general, the data will be random, it could consist of short repeating sequences of high's or low's, even if the data is scrambled. This will in turn force the error term to appear to not be locked, unless you average the error term over some time, in which if the data has zero mean, then the error term should have zero mean, then you would be locked?
determining if the DPLL is "locked"
Started by ●October 7, 2011
Reply by ●October 7, 20112011-10-07
On Oct 7, 1:41�pm, "jacobfenton" <jacob.fenton@n_o_s_p_a_m.gmail.com> wrote:> When a DPLL is used specifically for symbol timing sync (early-late > method), how does one determine if it is locked? Since in general, the data > will be random, it could consist of short repeating sequences of high's or > low's, even if the data is scrambled. This will in turn force the error > term to appear to not be locked, unless you average the error term over > some time, in which if the data has zero mean, then the error term should > have zero mean, then you would be locked?"unless you average the error term" Yes - and that averaging time is more or less related to the PLL bandwidth.
Reply by ●October 7, 20112011-10-07
On Fri, 07 Oct 2011 12:41:46 -0500, jacobfenton wrote:> When a DPLL is used specifically for symbol timing sync (early-late > method), how does one determine if it is locked? Since in general, the > data will be random, it could consist of short repeating sequences of > high's or low's, even if the data is scrambled. This will in turn force > the error term to appear to not be locked, unless you average the error > term over some time, in which if the data has zero mean, then the error > term should have zero mean, then you would be locked?If you construct your DPLL correctly there should be no error feedback at all when there are no transitions to be seen. In general one looks for some statistic based on the average error term to fall below some threshold. I find that what generally works best is either a running average or a 1st-order low-pass of the absolute value of the error. Keep in mind that given enough noise your loop can appear to be unlocked, even though it's tracking as solidly as can be. -- www.wescottdesign.com
Reply by ●October 7, 20112011-10-07
On Fri, 07 Oct 2011 15:48:43 -0500, Tim Wescott <tim@seemywebsite.com> wrote:>On Fri, 07 Oct 2011 12:41:46 -0500, jacobfenton wrote: > >> When a DPLL is used specifically for symbol timing sync (early-late >> method), how does one determine if it is locked? Since in general, the >> data will be random, it could consist of short repeating sequences of >> high's or low's, even if the data is scrambled. This will in turn force >> the error term to appear to not be locked, unless you average the error >> term over some time, in which if the data has zero mean, then the error >> term should have zero mean, then you would be locked? > >If you construct your DPLL correctly there should be no error feedback at >all when there are no transitions to be seen. > >In general one looks for some statistic based on the average error term >to fall below some threshold. I find that what generally works best is >either a running average or a 1st-order low-pass of the absolute value of >the error. Keep in mind that given enough noise your loop can appear to >be unlocked, even though it's tracking as solidly as can be.+1 on Tim's input. This is harder than it looks, enough so that I've avoided using this technique whenever possible, e.g., when the presence of framing indicators or FEC lock does the job instead. If those options aren't available then sometimes the loop statistics have to be used, but in my experience there are usually other methods that are simpler and more reliable. Eric Jacobsen Anchor Hill Communications www.anchorhill.com
Reply by ●October 7, 20112011-10-07
jacobfenton wrote:> When a DPLL is used specifically for symbol timing sync (early-late > method), how does one determine if it is locked? Since in general, the data > will be random, it could consist of short repeating sequences of high's or > low's, even if the data is scrambled. This will in turn force the error > term to appear to not be locked, unless you average the error term over > some time, in which if the data has zero mean, then the error term should > have zero mean, then you would be locked?The PLL is locked if the frequency error does not exhibit a DC bias. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●October 7, 20112011-10-07
On Oct 7, 7:34�pm, Vladimir Vassilevsky <nos...@nowhere.com> wrote:> jacobfenton wrote: > > When a DPLL is used specifically for symbol timing sync (early-late > > method), how does one determine if it is locked? Since in general, the data > > will be random, it could consist of short repeating sequences of high's or > > low's, even if the data is scrambled. This will in turn force the error > > term to appear to not be locked, unless you average the error term over > > some time, in which if the data has zero mean, then the error term should > > have zero mean, then you would be locked? > > The PLL is locked if the frequency error does not exhibit a DC bias. > > Vladimir Vassilevsky > DSP and Mixed Signal Design Consultanthttp://www.abvolt.comFor an analog loop this is not strictly true. A loop can be unstable with the carrier frequency swinging wildly above and below the desired frequency, however, the average error voltage could still be zero. I think a more formal definition of lock has to do with carrier cycle slippage.
Reply by ●October 7, 20112011-10-07
On 10/7/2011 7:34 PM, Vladimir Vassilevsky wrote:> > > jacobfenton wrote: > >> When a DPLL is used specifically for symbol timing sync (early-late >> method), how does one determine if it is locked? Since in general, the >> data >> will be random, it could consist of short repeating sequences of >> high's or >> low's, even if the data is scrambled. This will in turn force the error >> term to appear to not be locked, unless you average the error term over >> some time, in which if the data has zero mean, then the error term should >> have zero mean, then you would be locked? > > The PLL is locked if the frequency error does not exhibit a DC bias.With some analog loops, there will be DC if the natural frequency of the oscillator differs from the frequency it is locked to. Jerry -- Engineering is the art of making what you want from things you can get.
Reply by ●October 7, 20112011-10-07
Tim Wescott wrote:> In general one looks for some statistic based on the average error term > to fall below some threshold. I find that what generally works best is > either a running average or a 1st-order low-pass of the absolute value of > the error.The measurements of RMS error of phase are screwed up by ISI and noise. It could be hard to get any reliable indication of lock from there even with decision assisted algorithm.> Keep in mind that given enough noise your loop can appear to > be unlocked, even though it's tracking as solidly as can be.Exactly. Use the frequency error as criteria. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●October 7, 20112011-10-07
On Oct 7, 9:38�pm, Jerry Avins <j...@ieee.org> wrote:> On 10/7/2011 7:34 PM, Vladimir Vassilevsky wrote: > > > > > jacobfenton wrote: > > >> When a DPLL is used specifically for symbol timing sync (early-late > >> method), how does one determine if it is locked? Since in general, the > >> data > >> will be random, it could consist of short repeating sequences of > >> high's or > >> low's, even if the data is scrambled. This will in turn force the error > >> term to appear to not be locked, unless you average the error term over > >> some time, in which if the data has zero mean, then the error term should > >> have zero mean, then you would be locked? > > > The PLL is locked if the frequency error does not exhibit a DC bias. > > With some analog loops, there will be DC if the natural frequency of the > oscillator differs from the frequency it is locked to. >but then you don't have phase locking, so i don't quite get it. discarding the D (i don't think it should make any difference whether it's D or A), if it's a PLL it has a phase discriminator with an output that, when it's a DC value, controls an NCO or VCO. if it's locked, that's a DC (maybe not zero) value. so wouldn't something like the RMS of the output of a differentiator on the output of the phase discriminator be some measure of the degree of "locked" it is? you might have to do something about unwrapping, if the output of the discriminator is something like phase. i dunno what you would do if it's tracking a changing frequency. it might be locked but as the tracked frequency increases and decreases, the phase difference might sway both sides of what's nominal. r b-j
Reply by ●October 8, 20112011-10-08
On 10/7/2011 10:12 PM, robert bristow-johnson wrote:> On Oct 7, 9:38 pm, Jerry Avins<j...@ieee.org> wrote: >> On 10/7/2011 7:34 PM, Vladimir Vassilevsky wrote: >> >> >> >>> jacobfenton wrote: >> >>>> When a DPLL is used specifically for symbol timing sync (early-late >>>> method), how does one determine if it is locked? Since in general, the >>>> data >>>> will be random, it could consist of short repeating sequences of >>>> high's or >>>> low's, even if the data is scrambled. This will in turn force the error >>>> term to appear to not be locked, unless you average the error term over >>>> some time, in which if the data has zero mean, then the error term should >>>> have zero mean, then you would be locked? >> >>> The PLL is locked if the frequency error does not exhibit a DC bias. >> >> With some analog loops, there will be DC if the natural frequency of the >> oscillator differs from the frequency it is locked to. >> > > but then you don't have phase locking, so i don't quite get it. > > discarding the D (i don't think it should make any difference whether > it's D or A), if it's a PLL it has a phase discriminator with an > output that, when it's a DC value, controls an NCO or VCO. if it's > locked, that's a DC (maybe not zero) value. so wouldn't something > like the RMS of the output of a differentiator on the output of the > phase discriminator be some measure of the degree of "locked" it is? > you might have to do something about unwrapping, if the output of the > discriminator is something like phase. > > i dunno what you would do if it's tracking a changing frequency. it > might be locked but as the tracked frequency increases and decreases, > the phase difference might sway both sides of what's nominal.Right on all counts. The lock is to a phase offset that depends on frequency, but they're called PLLs nonetheless. Of course, an integrator fixes that, but it's not always warranted and sometimes degrades stability of lock acquisition. Jerry -- Engineering is the art of making what you want from things you can get.
