On Oct 7, 7:12�pm, robert bristow-johnson <r...@audioimagination.com> wrote:> On Oct 7, 9:38�pm, Jerry Avins <j...@ieee.org> wrote: > > > > > > > On 10/7/2011 7:34 PM, Vladimir Vassilevsky wrote: > > > > jacobfenton wrote: > > > >> When a DPLL is used specifically for symbol timing sync (early-late > > >> method), how does one determine if it is locked? Since in general, the > > >> data > > >> will be random, it could consist of short repeating sequences of > > >> high's or > > >> low's, even if the data is scrambled. This will in turn force the error > > >> term to appear to not be locked, unless you average the error term over > > >> some time, in which if the data has zero mean, then the error term should > > >> have zero mean, then you would be locked? > > > > The PLL is locked if the frequency error does not exhibit a DC bias. > > > With some analog loops, there will be DC if the natural frequency of the > > oscillator differs from the frequency it is locked to. > > but then you don't have phase locking, so i don't quite get it. > > discarding the D (i don't think it should make any difference whether > it's D or A), if it's a PLL it has a phase discriminator with an > output that, when it's a DC value, controls an NCO or VCO. �if it's > locked, that's a DC (maybe not zero) value. �so wouldn't something > like the RMS of the output of a differentiator on the output of the > phase discriminator be some measure of the degree of "locked" it is? > you might have to do something about unwrapping, if the output of the > discriminator is something like phase. > > i dunno what you would do if it's tracking a changing frequency. �it > might be locked but as the tracked frequency increases and decreases, > the phase difference might sway both sides of what's nominal. > > r b-j- Hide quoted text - > > - Show quoted text -From a hardware stand point, how the error signal is detected matters. If it�s picked off a single ended detector the offset has to be accounted for. If it�s a true differential out and run into a comparator then it�s directly useable as a lock indicator. If the loop has lost lock as a function sequence input than the input has caused the loop to break simply because it busted the track range. Fix the tracking range. Correct, it doesn�t matter whether it�s a D or A --- the concept is the same.
determining if the DPLL is "locked"
Started by ●October 7, 2011
Reply by ●October 8, 20112011-10-08
Reply by ●October 8, 20112011-10-08
On Fri, 7 Oct 2011 19:12:51 -0700 (PDT), robert bristow-johnson <rbj@audioimagination.com> wrote:>On Oct 7, 9:38=A0pm, Jerry Avins <j...@ieee.org> wrote: >> On 10/7/2011 7:34 PM, Vladimir Vassilevsky wrote: >> >> >> >> > jacobfenton wrote: >> >> >> When a DPLL is used specifically for symbol timing sync (early-late >> >> method), how does one determine if it is locked? Since in general, the >> >> data >> >> will be random, it could consist of short repeating sequences of >> >> high's or >> >> low's, even if the data is scrambled. This will in turn force the erro= >r >> >> term to appear to not be locked, unless you average the error term ove= >r >> >> some time, in which if the data has zero mean, then the error term sho= >uld >> >> have zero mean, then you would be locked? >> >> > The PLL is locked if the frequency error does not exhibit a DC bias. >> >> With some analog loops, there will be DC if the natural frequency of the >> oscillator differs from the frequency it is locked to. >> > >but then you don't have phase locking, so i don't quite get it. > >discarding the D (i don't think it should make any difference whether >it's D or A), if it's a PLL it has a phase discriminator with an >output that, when it's a DC value, controls an NCO or VCO. if it's >locked, that's a DC (maybe not zero) value. so wouldn't something >like the RMS of the output of a differentiator on the output of the >phase discriminator be some measure of the degree of "locked" it is? >you might have to do something about unwrapping, if the output of the >discriminator is something like phase. > >i dunno what you would do if it's tracking a changing frequency. it >might be locked but as the tracked frequency increases and decreases, >the phase difference might sway both sides of what's nominal. > >r b-jI think two things have been confused here. The phase detector output should strictly discriminate phase, although there are such things as phase-frequency detectors. Regardless, a DC offset at the output of the phase discriminator (for something like a Costas loop or the mentioned early-late symbol timing loop) generally indicates an unlocked condition due to a frequency offset. What was said above was that the frequency "error" is zero when the loop is locked, which is true, but there's not typically an easy way to detect that. In a second-order loop the integrator contents can be zero when the loop is locked or unlocked, and can be non-zero when the loop is locked or unlocked. Knowing the true frequency of the signal can be determined once it is determined that lock has been achieved, but it's a bit of a chicken-and-egg problem trying to use frequency error as a lock criterion unless the transmitted frequency offset is somehow known a-priori. At high SNR it is possible to use loop statistics as a lock indicator, but in dynamic or low SNR conditions I've found it not worth the effort. There's almost always a better way to do it. Eric Jacobsen Anchor Hill Communications www.anchorhill.com
Reply by ●October 8, 20112011-10-08
On Oct 8, 12:24�am, Jerry Avins <j...@ieee.org> wrote:> On 10/7/2011 10:12 PM, robert bristow-johnson wrote: > > > > > On Oct 7, 9:38 pm, Jerry Avins<j...@ieee.org> �wrote: > >> On 10/7/2011 7:34 PM, Vladimir Vassilevsky wrote: > > >>> jacobfenton wrote: > > >>>> When a DPLL is used specifically for symbol timing sync (early-late > >>>> method), how does one determine if it is locked? Since in general, the > >>>> data > >>>> will be random, it could consist of short repeating sequences of > >>>> high's or > >>>> low's, even if the data is scrambled. This will in turn force the error > >>>> term to appear to not be locked, unless you average the error term over > >>>> some time, in which if the data has zero mean, then the error term should > >>>> have zero mean, then you would be locked? > > >>> The PLL is locked if the frequency error does not exhibit a DC bias. > > >> With some analog loops, there will be DC if the natural frequency of the > >> oscillator differs from the frequency it is locked to. > > > but then you don't have phase locking, so i don't quite get it. > > > discarding the D (i don't think it should make any difference whether > > it's D or A), if it's a PLL it has a phase discriminator with an > > output that, when it's a DC value, controls an NCO or VCO. �if it's > > locked, that's a DC (maybe not zero) value. �so wouldn't something > > like the RMS of the output of a differentiator on the output of the > > phase discriminator be some measure of the degree of "locked" it is? > > you might have to do something about unwrapping, if the output of the > > discriminator is something like phase. > > > i dunno what you would do if it's tracking a changing frequency. �it > > might be locked but as the tracked frequency increases and decreases, > > the phase difference might sway both sides of what's nominal. > > Right on all counts. The lock is to a phase offset that depends on > frequency, but they're called PLLs nonetheless. Of course, an integrator > fixes that, but it's not always warranted and sometimes degrades > stability of lock acquisition. >well, the VCO or NCO does integrate its input to result in phase. so there is an integrator in the loop if the discriminator is a *phase* discriminator rather than a frequency discriminator. putting in an additional integrator doesn't sound to me to be such a good idea. but my point is that, if the frequency of the VCO or NCO is not zero, *and* there isn't this extra integrator in the controller (the controller is proportional), then the output of the phase discriminator must also be non-zero. it might be that the higher the frequency, the more offset is the phases of the two signals (resulting in a larger phase discriminator output and a larger DC value going into the VCO or NCO), but if the frequency is constant, that phase discriminator output is *not* zero, yet it's locked. r b-j
Reply by ●October 8, 20112011-10-08
On Oct 8, 11:19�am, eric.jacob...@ieee.org (Eric Jacobsen) wrote:> On Fri, 7 Oct 2011 19:12:51 -0700 (PDT), robert bristow-johnson > > > > <r...@audioimagination.com> wrote: > >On Oct 7, 9:38=A0pm, Jerry Avins <j...@ieee.org> wrote: > >> On 10/7/2011 7:34 PM, Vladimir Vassilevsky wrote: > > >> > jacobfenton wrote: > > >> >> When a DPLL is used specifically for symbol timing sync (early-late > >> >> method), how does one determine if it is locked? Since in general, the > >> >> data > >> >> will be random, it could consist of short repeating sequences of > >> >> high's or > >> >> low's, even if the data is scrambled. This will in turn force the erro= > >r > >> >> term to appear to not be locked, unless you average the error term ove= > >r > >> >> some time, in which if the data has zero mean, then the error term sho= > >uld > >> >> have zero mean, then you would be locked? > > >> > The PLL is locked if the frequency error does not exhibit a DC bias. > > >> With some analog loops, there will be DC if the natural frequency of the > >> oscillator differs from the frequency it is locked to. > > >but then you don't have phase locking, so i don't quite get it. > > >discarding the D (i don't think it should make any difference whether > >it's D or A), if it's a PLL it has a phase discriminator with an > >output that, when it's a DC value, controls an NCO or VCO. �if it's > >locked, that's a DC (maybe not zero) value. �so wouldn't something > >like the RMS of the output of a differentiator on the output of the > >phase discriminator be some measure of the degree of "locked" it is? > >you might have to do something about unwrapping, if the output of the > >discriminator is something like phase. > > >i dunno what you would do if it's tracking a changing frequency. �it > >might be locked but as the tracked frequency increases and decreases, > >the phase difference might sway both sides of what's nominal. > > I think two things have been confused here. � The phase detector > output should strictly discriminate phase, although there are such > things as phase-frequency detectors. � Regardless, a DC offset at the > output of the phase discriminator (for something like a Costas loop or > the mentioned early-late symbol timing loop) generally indicates an > unlocked condition due to a frequency offset. >then there has to be an additional integrator in the loop to raise or lower the VCO or NCO input (as non-zero DC values) to integrate out any non-zero phase error. but if there is no integrator (besides the one inherent to the VCO or NCO) in the loop, the input to the VCO or NCO has to be non-zero for a non-zero frequency and that has to be proportional to the output of the phase discriminator. no? r b-j
Reply by ●October 8, 20112011-10-08
On Oct 8, 10:54�am, robert bristow-johnson <r...@audioimagination.com> wrote:> On Oct 8, 11:19�am, eric.jacob...@ieee.org (Eric Jacobsen) wrote: > > > > > > > On Fri, 7 Oct 2011 19:12:51 -0700 (PDT), robert bristow-johnson > > > <r...@audioimagination.com> wrote: > > >On Oct 7, 9:38=A0pm, Jerry Avins <j...@ieee.org> wrote: > > >> On 10/7/2011 7:34 PM, Vladimir Vassilevsky wrote: > > > >> > jacobfenton wrote: > > > >> >> When a DPLL is used specifically for symbol timing sync (early-late > > >> >> method), how does one determine if it is locked? Since in general, the > > >> >> data > > >> >> will be random, it could consist of short repeating sequences of > > >> >> high's or > > >> >> low's, even if the data is scrambled. This will in turn force the erro= > > >r > > >> >> term to appear to not be locked, unless you average the error term ove= > > >r > > >> >> some time, in which if the data has zero mean, then the error term sho= > > >uld > > >> >> have zero mean, then you would be locked? > > > >> > The PLL is locked if the frequency error does not exhibit a DC bias. > > > >> With some analog loops, there will be DC if the natural frequency of the > > >> oscillator differs from the frequency it is locked to. > > > >but then you don't have phase locking, so i don't quite get it. > > > >discarding the D (i don't think it should make any difference whether > > >it's D or A), if it's a PLL it has a phase discriminator with an > > >output that, when it's a DC value, controls an NCO or VCO. �if it's > > >locked, that's a DC (maybe not zero) value. �so wouldn't something > > >like the RMS of the output of a differentiator on the output of the > > >phase discriminator be some measure of the degree of "locked" it is? > > >you might have to do something about unwrapping, if the output of the > > >discriminator is something like phase. > > > >i dunno what you would do if it's tracking a changing frequency. �it > > >might be locked but as the tracked frequency increases and decreases, > > >the phase difference might sway both sides of what's nominal. > > > I think two things have been confused here. � The phase detector > > output should strictly discriminate phase, although there are such > > things as phase-frequency detectors. � Regardless, a DC offset at the > > output of the phase discriminator (for something like a Costas loop or > > the mentioned early-late symbol timing loop) generally indicates an > > unlocked condition due to a frequency offset. > > then there has to be an additional integrator in the loop to raise or > lower the VCO or NCO input (as non-zero DC values) to integrate out > any non-zero phase error. �but if there is no integrator (besides the > one inherent to the VCO or NCO) in the loop, the input to the VCO or > NCO has to be non-zero for a non-zero frequency and that has to be > proportional to the output of the phase discriminator. �no? > > r b-j- Hide quoted text - > > - Show quoted text -Is there something inherent in the early-late gate topology that prevents a compensator from being used?
Reply by ●October 9, 20112011-10-09
On Oct 8, 3:37�pm, me0...@yahoo.com wrote:> On Oct 8, 10:54�am, robert bristow-johnson <r...@audioimagination.com> > wrote: > > > > > On Oct 8, 11:19�am, eric.jacob...@ieee.org (Eric Jacobsen) wrote: > > > > On Fri, 7 Oct 2011 19:12:51 -0700 (PDT), robert bristow-johnson > > > > <r...@audioimagination.com> wrote: > > > >On Oct 7, 9:38=A0pm, Jerry Avins <j...@ieee.org> wrote: > > > >> On 10/7/2011 7:34 PM, Vladimir Vassilevsky wrote: > > > > >> > jacobfenton wrote: > > > > >> >> When a DPLL is used specifically for symbol timing sync (early-late > > > >> >> method), how does one determine if it is locked? Since in general, the > > > >> >> data > > > >> >> will be random, it could consist of short repeating sequences of > > > >> >> high's or > > > >> >> low's, even if the data is scrambled. This will in turn force the erro= > > > >r > > > >> >> term to appear to not be locked, unless you average the error term ove= > > > >r > > > >> >> some time, in which if the data has zero mean, then the error term sho= > > > >uld > > > >> >> have zero mean, then you would be locked? > > > > >> > The PLL is locked if the frequency error does not exhibit a DC bias. > > > > >> With some analog loops, there will be DC if the natural frequency of the > > > >> oscillator differs from the frequency it is locked to. > > > > >but then you don't have phase locking, so i don't quite get it. > > > > >discarding the D (i don't think it should make any difference whether > > > >it's D or A), if it's a PLL it has a phase discriminator with an > > > >output that, when it's a DC value, controls an NCO or VCO. �if it's > > > >locked, that's a DC (maybe not zero) value. �so wouldn't something > > > >like the RMS of the output of a differentiator on the output of the > > > >phase discriminator be some measure of the degree of "locked" it is? > > > >you might have to do something about unwrapping, if the output of the > > > >discriminator is something like phase. > > > > >i dunno what you would do if it's tracking a changing frequency. �it > > > >might be locked but as the tracked frequency increases and decreases, > > > >the phase difference might sway both sides of what's nominal. > > > > I think two things have been confused here. � The phase detector > > > output should strictly discriminate phase, although there are such > > > things as phase-frequency detectors. � Regardless, a DC offset at the > > > output of the phase discriminator (for something like a Costas loop or > > > the mentioned early-late symbol timing loop) generally indicates an > > > unlocked condition due to a frequency offset. > > > then there has to be an additional integrator in the loop to raise or > > lower the VCO or NCO input (as non-zero DC values) to integrate out > > any non-zero phase error. �but if there is no integrator (besides the > > one inherent to the VCO or NCO) in the loop, the input to the VCO or > > NCO has to be non-zero for a non-zero frequency and that has to be > > proportional to the output of the phase discriminator. �no? > > Is there something inherent in the early-late gate topology that > prevents a compensator from being used?i dunno what that means. what compensator do you mean? still mulling what Eric had said. r b-j
Reply by ●October 11, 20112011-10-11
>On Fri, 07 Oct 2011 15:48:43 -0500, Tim Wescott <tim@seemywebsite.com> >wrote: > >>On Fri, 07 Oct 2011 12:41:46 -0500, jacobfenton wrote: >> >>> When a DPLL is used specifically for symbol timing sync (early-late >>> method), how does one determine if it is locked? Since in general, the >>> data will be random, it could consist of short repeating sequences of >>> high's or low's, even if the data is scrambled. This will in turnforce>>> the error term to appear to not be locked, unless you average theerror>>> term over some time, in which if the data has zero mean, then theerror>>> term should have zero mean, then you would be locked? >> >>If you construct your DPLL correctly there should be no error feedback at>>all when there are no transitions to be seen. >> >>In general one looks for some statistic based on the average error term >>to fall below some threshold. I find that what generally works best is >>either a running average or a 1st-order low-pass of the absolute value of>>the error. Keep in mind that given enough noise your loop can appear to>>be unlocked, even though it's tracking as solidly as can be. > >+1 on Tim's input. This is harder than it looks, enough so that >I've avoided using this technique whenever possible, e.g., when the >presence of framing indicators or FEC lock does the job instead. If >those options aren't available then sometimes the loop statistics have >to be used, but in my experience there are usually other methods that >are simpler and more reliable. > > >Eric Jacobsen >Anchor Hill Communications >www.anchorhill.com >Yes, this does make sense, using FEC or something would be a much easier indicator.
