Forums

IIR fixed-point implementation

Started by Benjamin Couillard November 14, 2011
HI everyone,

I was wondering if anyone can recommend me good books or papers on
fixed-point IIR implementation strategies on FPGAs or CPUs. Especially
regarding fc versus Fs and coefficient quantization. I have issues
with an order-1 DC-removal filter with Fs = 100 MHz and Fcut = 250
kHz. Basically, I need lots of precision in the intermediate
calculations which impact the number of bits for the multiplier and
thus the maximum frequency of my FPGA design.

Best regards
On 11/14/2011 1:15 PM, Benjamin Couillard wrote:
> HI everyone, > > I was wondering if anyone can recommend me good books or papers on > fixed-point IIR implementation strategies on FPGAs or CPUs. Especially > regarding fc versus Fs and coefficient quantization. I have issues > with an order-1 DC-removal filter with Fs = 100 MHz and Fcut = 250 > kHz. Basically, I need lots of precision in the intermediate > calculations which impact the number of bits for the multiplier and > thus the maximum frequency of my FPGA design. > > Best regards
My experience has been second-order sections implemented on the classic direct form models have a very hard time handling "very-lowpass" filters, i.e. Fc < 1/100 Fs. Check out http://www.earlevel.com/main/2003/03/02/the-digital-state-variable-filter/ , which discusses the Chamberlin form second-order section. It's a direct rip-off of the classic analog bi-quad. At higher Fc's this plan develops problems as the difference between your digital and analog frequencies become pronounced, but down where you're operating it's a very nice way to go about it. With a little pushing blocks around, you can get it down to two multiples, one by f^2 and one by fq. The really nice thing here is that you can use any old analog filter design program to get your per-stage Fs and Qs (I use TI FilterPro, the price is right), then translate them straight into their digital equivalents and move on. As a point of reference, I just used this technique to implement a 16-bit 200 Hz 4-pole Bessel filter on a 15.625 ksps data stream with only an 18x27 multiplier and 36-bit internal data states. A little more massaging could have probably gotten it down to only using an 18x18 multiply, but I was running out of calendar faster than I was running out of FPGA resources. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.

Benjamin Couillard wrote:

> HI everyone, > > I was wondering if anyone can recommend me good books or papers on > fixed-point IIR implementation strategies on FPGAs or CPUs. Especially > regarding fc versus Fs and coefficient quantization.
Dietrich Schlichtharle. Digital Filters: Basics and Design. ISBN 3-540-66841-1
> I have issues > with an order-1 DC-removal filter with Fs = 100 MHz and Fcut = 250 > kHz.
That should be no problem. Loss of precision ~ 2PiFc/Fs ~ 6 bits.
> Basically, I need lots of precision in the intermediate > calculations which impact the number of bits for the multiplier and > thus the maximum frequency of my FPGA design.
Need no multiplication. This filter implements with trivial math: int filter(int x) { static int z; int output = x - z; z += output >> 6; return output; } //---------------- Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
On Mon, 14 Nov 2011 13:57:42 -0800, Rob Gaddi wrote:

> On 11/14/2011 1:15 PM, Benjamin Couillard wrote: >> HI everyone, >> >> I was wondering if anyone can recommend me good books or papers on >> fixed-point IIR implementation strategies on FPGAs or CPUs. Especially >> regarding fc versus Fs and coefficient quantization. I have issues with >> an order-1 DC-removal filter with Fs = 100 MHz and Fcut = 250 kHz. >> Basically, I need lots of precision in the intermediate calculations >> which impact the number of bits for the multiplier and thus the maximum >> frequency of my FPGA design. >> >> Best regards > > My experience has been second-order sections implemented on the classic > direct form models have a very hard time handling "very-lowpass" > filters, i.e. Fc < 1/100 Fs. > > Check out > http://www.earlevel.com/main/2003/03/02/the-digital-state-variable-
filter/
> , which discusses the Chamberlin form second-order section. It's a > direct rip-off of the classic analog bi-quad. At higher Fc's this plan > develops problems as the difference between your digital and analog > frequencies become pronounced, but down where you're operating it's a > very nice way to go about it. With a little pushing blocks around, you > can get it down to two multiples, one by f^2 and one by fq. > > The really nice thing here is that you can use any old analog filter > design program to get your per-stage Fs and Qs (I use TI FilterPro, the > price is right), then translate them straight into their digital > equivalents and move on. > > As a point of reference, I just used this technique to implement a > 16-bit 200 Hz 4-pole Bessel filter on a 15.625 ksps data stream with > only an 18x27 multiplier and 36-bit internal data states. A little more > massaging could have probably gotten it down to only using an 18x18 > multiply, but I was running out of calendar faster than I was running > out of FPGA resources.
Rearranging the blocks for fq and f^2 isn't going to help with coefficient quantization at all, although it does help with real estate. -- www.wescottdesign.com
On Mon, 14 Nov 2011 13:15:07 -0800, Benjamin Couillard wrote:

> HI everyone, > > I was wondering if anyone can recommend me good books or papers on > fixed-point IIR implementation strategies on FPGAs or CPUs. Especially > regarding fc versus Fs and coefficient quantization. I have issues with > an order-1 DC-removal filter with Fs = 100 MHz and Fcut = 250 kHz. > Basically, I need lots of precision in the intermediate calculations > which impact the number of bits for the multiplier and thus the maximum > frequency of my FPGA design.
How accurate do you need the cutoff frequency to be? For a 1st-order filter in particular you only need coefficient precision to get precision in your cutoff frequency -- at the extreme you can just shift your filter output down by 8 and subtract from your accumulator. This gives you a cutoff frequency of 153kHz instead of 250kHz. You do still need the 8 bits of extra accumulator precision to accommodate the 400:1 ratio of Fs to Fcut, but if you don't mind that error in cutoff frequency can get away with no real multiplication at all. If you _do_ mind the cutoff frequency error then you may be able to get away with a truncated multiply (assuming that you're not just planning on using a multiplier block). -- www.wescottdesign.com
On 11/14/11 4:15 PM, Benjamin Couillard wrote:
> > I was wondering if anyone can recommend me good books or papers on > fixed-point IIR implementation strategies on FPGAs or CPUs. Especially > regarding fc versus Fs and coefficient quantization. I have issues > with an order-1 DC-removal filter with Fs = 100 MHz and Fcut = 250 > kHz. Basically, I need lots of precision in the intermediate > calculations which impact the number of bits for the multiplier and > thus the maximum frequency of my FPGA design. >
lemme see, 1. fixed point 2. DC blocking filter 3. 1st order 4. quantization problems you might wanna check out: http://www.dspguru.com/dsp/tricks/fixed-point-dc-blocking-filter-with-noise-shaping the other thing you wanna do is to is to represent the transfer function in terms of 1-cos(2*pi*Fcut/Fs), instead of just the cos(). there is a nice trig identity for that. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge."
On 11/14/11 6:18 PM, robert bristow-johnson wrote:
> On 11/14/11 4:15 PM, Benjamin Couillard wrote: >> >> I was wondering if anyone can recommend me good books or papers on >> fixed-point IIR implementation strategies on FPGAs or CPUs. Especially >> regarding fc versus Fs and coefficient quantization. I have issues >> with an order-1 DC-removal filter with Fs = 100 MHz and Fcut = 250 >> kHz. Basically, I need lots of precision in the intermediate >> calculations which impact the number of bits for the multiplier and >> thus the maximum frequency of my FPGA design. >> > > lemme see, > > 1. fixed point > 2. DC blocking filter > 3. 1st order > 4. quantization problems > > you might wanna check out: > > > http://www.dspguru.com/dsp/tricks/fixed-point-dc-blocking-filter-with-noise-shaping > > > the other thing you wanna do is to is to represent the transfer function > in terms of 1-cos(2*pi*Fcut/Fs), instead of just the cos(). there is a > nice trig identity for that. >
ya know, i just remembered that, way back when, Tim did a simpler, more efficient version of this: http://groups.google.com/group/comp.dsp/msg/3759bc4014951a03 -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge."
On Mon, 14 Nov 2011 13:15:07 -0800 (PST), Benjamin Couillard
<benjamin.couillard@gmail.com> wrote:

>HI everyone, > >I was wondering if anyone can recommend me good books or papers on >fixed-point IIR implementation strategies on FPGAs or CPUs. Especially >regarding fc versus Fs and coefficient quantization. I have issues >with an order-1 DC-removal filter with Fs = 100 MHz and Fcut = 250 >kHz. Basically, I need lots of precision in the intermediate >calculations which impact the number of bits for the multiplier and >thus the maximum frequency of my FPGA design. > >Best regards
Hello Benjamin, I haven't read all the replies in this thread but it occurred to me that the following web pages may be interesting to you. For an idea about a linear-phase DC-removal filter see: http://www.dsprelated.com/showarticle/58.php For an idea on how to implement very narrowband lowpass IIR filters, you might take a look at: http://www.dsprelated.com/showarticle/120.php Good Luck, [-Rick-]
On 15 nov, 07:24, Rick Lyons <R.Lyons@_BOGUS_ieee.org> wrote:
> On Mon, 14 Nov 2011 13:15:07 -0800 (PST), Benjamin Couillard > > <benjamin.couill...@gmail.com> wrote: > >HI everyone, > > >I was wondering if anyone can recommend me good books or papers on > >fixed-point IIR implementation strategies on FPGAs or CPUs. Especially > >regarding fc versus Fs and coefficient quantization. I have issues > >with an order-1 DC-removal filter with Fs = 100 MHz and Fcut = 250 > >kHz. Basically, I need lots of precision in the intermediate > >calculations which impact the number of bits for the multiplier and > >thus the maximum frequency of my FPGA design. > > >Best regards > > Hello Benjamin, > &#2013266080; I haven't read all the replies in this thread but > it occurred to me that the following web pages may > be interesting to you. &#2013266080;For an idea about a > linear-phase DC-removal filter see: > > http://www.dsprelated.com/showarticle/58.php > > For an idea on how to implement very narrowband > lowpass IIR filters, you might take a look at: > > http://www.dsprelated.com/showarticle/120.php > > Good Luck, > [-Rick-]
Thank you Rck, it's a really interesting technique.