Phase detector choice - I*Q vs arctan(Q/I). arctan(Q/I) never locks.

On Mon, 28 Nov 2011 09:11:37 -0800, Rune Allnor wrote:

> On 28 Nov, 04:16, Tim Wescott <t...@seemywebsite.com> wrote:
>> On Sun, 27 Nov 2011 20:46:39 -0600, johnlovestohate wrote:
> 
>> > Any suggestions?
>>
>> Try simulating it with a really low SNR test signal -- that'll let you
>> see what it's supposed to be, then you can go from there.
> 
> *Low* SNR?

Uh, would you believe that this is International Backwards Week?

No?  Oh well -- D'OH!!

OP:

It really should work at _high_ SNR, if you haven't gotten your terms 
backwards.  You are aware that you need to use atan2(Q, I), and that it 
needs to be modulo pi, yes?  Because it's BPSK, "locked" means that the 
phase is at either 0 or pi; so your phase error is the phase relative to 
0 radians if it's close to 0 radians, and it needs to be the phase 
relative to pi radians if it's close to pi radians.

If you just use the phase, then you'll be wrong by pi radians half the 
time, and you'll never lock.

-- 
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

On 28 Nov, 20:04, Tim Wescott <t...@seemywebsite.com> wrote:
> On Mon, 28 Nov 2011 09:11:37 -0800, Rune Allnor wrote:
> > On 28 Nov, 04:16, Tim Wescott <t...@seemywebsite.com> wrote:
> >> On Sun, 27 Nov 2011 20:46:39 -0600, johnlovestohate wrote:
>
> >> > Any suggestions?
>
> >> Try simulating it with a really low SNR test signal -- that'll let you
> >> see what it's supposed to be, then you can go from there.
>
> > *Low* SNR?
>
> Uh, would you believe that this is International Backwards Week?
>
> No? &#4294967295;Oh well -- D'OH!!

Just asking; there are so many weird or worse schemes
out there...

Rune

On Nov 28, 2:04&#4294967295;pm, Tim Wescott <t...@seemywebsite.com> wrote:
> Because it's BPSK, "locked" means that the
> phase is at either 0 or pi; so your phase error is the phase relative to
> 0 radians if it's close to 0 radians, and it needs to be the phase
> relative to pi radians if it's close to pi radians.
>
> If you just use the phase, then you'll be wrong by pi radians half the
> time, and you'll never lock.

Shouldn't a good PLL be forever trying to catch up
as the phase changes back and forth between 0 and
pi at the bit transitions, and thus _not_ be in lock in
the vicinity of (and especially right after) the bit
transitions?  It would then slowly get back into lock
(assuming a low data rate and plenty of time between
bit transitions) and then have to do it all over again
when the bit changes.  Some people avoid this by
tracking the double-frequency signal obtained by
squaring the BPSK signal, and ameliorating the
effects of the phase ambiguity (the loop might
lock on to sin(wt) or to -sin(wt)) by using differential
encoding.  Yes, differential encoding can be used
in plain vanilla phase-coherent BPSK also; it is not
restricted to DPSK schemes only.

Dilip Sarwate

On Mon, 28 Nov 2011 12:00:45 -0800, dvsarwate wrote:

> On Nov 28, 2:04&nbsp;pm, Tim Wescott <t...@seemywebsite.com> wrote:
>> Because it's BPSK, "locked" means that the phase is at either 0 or pi;
>> so your phase error is the phase relative to 0 radians if it's close to
>> 0 radians, and it needs to be the phase relative to pi radians if it's
>> close to pi radians.
>>
>> If you just use the phase, then you'll be wrong by pi radians half the
>> time, and you'll never lock.
> 
> Shouldn't a good PLL be forever trying to catch up as the phase changes
> back and forth between 0 and pi at the bit transitions, and thus _not_
> be in lock in the vicinity of (and especially right after) the bit
> transitions?  It would then slowly get back into lock (assuming a low
> data rate and plenty of time between bit transitions) and then have to
> do it all over again when the bit changes.  Some people avoid this by
> tracking the double-frequency signal obtained by squaring the BPSK
> signal, and ameliorating the effects of the phase ambiguity (the loop
> might lock on to sin(wt) or to -sin(wt)) by using differential encoding.
>  Yes, differential encoding can be used in plain vanilla phase-coherent
> BPSK also; it is not restricted to DPSK schemes only.

All the PSK demodulation schemes that I know of call for the carrier PLL 
to lock onto the hypothetical reference at the transmitter, which means 
that it is in lock when the received signal is at 0 or at pi, and the 
data is demodulated by beating against that carrier to give you a simple 
positive or negative number out of the detector.

-- 
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

On Nov 28, 4:13&#4294967295;pm, Tim Wescott <t...@seemywebsite.com> wrote:

> All the PSK demodulation schemes that I know of call for the carrier PLL
> to lock onto the hypothetical reference at the transmitter, which means
> that it is in lock when the received signal is at 0 or at pi, and the
> data is demodulated by beating against that carrier to give you a simple
> positive or negative number out of the detector.


So the question is: how does the PLL get at the hypothetical
reference at the transmitter?  All it sees is, say, a signal
A.sin(wt) from t = 0 till t = T, and then from t = T+ till t = 2T,
the signal might be A.sin(wt) again, or it might be -A.sin(wt).
How is the control input to the VCO produced to maintain
a steady drumbeat of sin(wt) regardless of possible changes
in phase of the received signal?  No problem, you say, there
is an initial training period during which there is no data
modulation and the PLL locks on to the carrier phase.  But
how does it maintain lock after the initial training period is
long past and the next training period is some time in the
future?  I suggest that the VCO control input is produced
by comparing double-frequency components (which do
not change phase when the data bit flips), and phase
ambiguity is an issue that needs to be resolved.  It might
be done by differential encoding or by using transparent
coding: codeword x and not(x), the bit by bit complement
of x, both represent the same data sequence, and so
regardless of phase ambiguity and whether the demodulator
produces x or not(x), the data sequence is recovered
correctly.

--Dilip Sarwate

On Mon, 28 Nov 2011 16:17:18 -0800 (PST), dvsarwate
<dvsarwate@yahoo.com> wrote:

>On Nov 28, 4:13=A0pm, Tim Wescott <t...@seemywebsite.com> wrote:
>
>> All the PSK demodulation schemes that I know of call for the carrier PLL
>> to lock onto the hypothetical reference at the transmitter, which means
>> that it is in lock when the received signal is at 0 or at pi, and the
>> data is demodulated by beating against that carrier to give you a simple
>> positive or negative number out of the detector.
>
>
>So the question is: how does the PLL get at the hypothetical
>reference at the transmitter?  All it sees is, say, a signal
>A.sin(wt) from t =3D 0 till t =3D T, and then from t =3D T+ till t =3D 2T,
>the signal might be A.sin(wt) again, or it might be -A.sin(wt).
>How is the control input to the VCO produced to maintain
>a steady drumbeat of sin(wt) regardless of possible changes
>in phase of the received signal?  No problem, you say, there
>is an initial training period during which there is no data
>modulation and the PLL locks on to the carrier phase.  But
>how does it maintain lock after the initial training period is
>long past and the next training period is some time in the
>future?  I suggest that the VCO control input is produced
>by comparing double-frequency components (which do
>not change phase when the data bit flips), and phase
>ambiguity is an issue that needs to be resolved.  It might
>be done by differential encoding or by using transparent
>coding: codeword x and not(x), the bit by bit complement
>of x, both represent the same data sequence, and so
>regardless of phase ambiguity and whether the demodulator
>produces x or not(x), the data sequence is recovered
>correctly.
>
>--Dilip Sarwate

Not sure I completely follow the proposed question, but in most
digital implementations the phase detector uses only one sample per
symbol, and the phase detector "aliases" or folds its response so that
it is periodic over the modulation order.   In other words, the phase
detector for BPSK will have zeros at 0 and 180 degrees and properly
signed proportional error signals as the received symbol deviates from
0 or 180 degrees.   This makes the loop independent of the data
sequence and it can track data as well as a training sequence (but
perhapse with half as much "capture" range on the phase).

Doubling the input frequency (via a nonlinearity or whatever) can be
made to work, but it often amplifies the input noise.   I don't know
of many modern implementations that do this.



Eric Jacobsen
Anchor Hill Communications
www.anchorhill.com

>On Mon, 28 Nov 2011 09:11:37 -0800, Rune Allnor wrote:
>
>> On 28 Nov, 04:16, Tim Wescott <t...@seemywebsite.com> wrote:
>>> On Sun, 27 Nov 2011 20:46:39 -0600, johnlovestohate wrote:
>> 
>>> > Any suggestions?
>>>
>>> Try simulating it with a really low SNR test signal -- that'll let you
>>> see what it's supposed to be, then you can go from there.
>> 
>> *Low* SNR?
>
>Uh, would you believe that this is International Backwards Week?
>
>No?  Oh well -- D'OH!!
>
>OP:
>
>It really should work at _high_ SNR, if you haven't gotten your terms 
>backwards.  You are aware that you need to use atan2(Q, I), and that it 
>needs to be modulo pi, yes?  Because it's BPSK, "locked" means that the 
>phase is at either 0 or pi; so your phase error is the phase relative to 
>0 radians if it's close to 0 radians, and it needs to be the phase 
>relative to pi radians if it's close to pi radians.
>

I failed to mention that I am in fact using atan2(Q,I) and it is modulo pi.
The following code describes what I do.

nco_out = expj(-phase); // expj(\phi) finds cos(\phi) + j*sin(\phi)
error = mod_pi(atan2(nco_out.imag(), nco_out.real()));

freq = freq + beta*error;
phase = phase + freq + alpha*error;

In the above code, I phase wrap the variable phase to lie between
(-2*pi,2*pi).

I see that the energy of the quadrature part reduces but never goes down to
zero.


>If you just use the phase, then you'll be wrong by pi radians half the 
>time, and you'll never lock.
>
>-- 
>My liberal friends think I'm a conservative kook.
>My conservative friends think I'm a liberal kook.
>Why am I not happy that they have found common ground?
>
>Tim Wescott, Communications, Control, Circuits & Software
>http://www.wescottdesign.com
>

On 11/27/2011 08:46 PM, johnlovestohate wrote:
> Hi,
> I implemented a second order phase locked loop with \alpha and \beta as the
> P&  I gains of the PI filter in use. I am trying to lock on a high SNR
> complex baseband signal with BPSK modulation. The signal amplitude is
> between {-1,1}. I can easily lock when I use I*Q phase detector and I limit
> the phase error to {-1,1}.
>
> When I use the arctan(Q/I) phase detector it never locks and the bit
> transitions seems to be causing the problem. I tried different loop
> bandwidths, alpha, beta values but I never see anything close to locking
> which would give me an intuition on locking with arctan() phase detection
> scheme.
>
> Any suggestions?
>
> Thanks

You're probably getting a 90-degree phase shift in one that's not in the 
other. Recheck your assumptions.

--Randy

On 29 Nov, 12:22, "johnlovestohate"
<aliatolemiss@n_o_s_p_a_m.gmail.com> wrote:

> I see that the energy of the quadrature part reduces but never goes down to
> zero.

That's what one would expect in noisy systems: One can
do very well, but not perfectly.

Rune