Using 2 ADCs

Hello,

I remember reading some time ago an article explaingng a technique using 2
ADCs fed with the same signal to and each runnig at
Fs - sampling frequency to digitize a signal  with frequencies from 0 up to
Fs (and not up to Fs/2)


I'm unable to find this article again.

Can  somebody please, explain me the technique or point me to a text
explaning it?


Thanks
Vadim

"Vadim Lebedev" <vadiml@libertysurf.fr> wrote in message
news:bsqpcc$b3k$1@news.tiscali.fr...
> Hello,
>
> I remember reading some time ago an article explaingng a technique using 2
> ADCs fed with the same signal to and each runnig at
> Fs - sampling frequency to digitize a signal  with frequencies from 0 up
to
> Fs (and not up to Fs/2)
>
>
> I'm unable to find this article again.
>
> Can  somebody please, explain me the technique or point me to a text
> explaning it?

Vadim,

Well, it has been rather common practice to use 2 ADCs when the maximum
sample rate capability of the ADCs was lower than the needed sample rate for
the signal.
Let's say you wanted to sample a signal at 120MHz and the ADCs are only good
to 80MHz.
If you put the same input into both the ADCs as you've mentioned, then clock
the ADCs at 60MHz, and 180 degrees out of phase, so that their samples
alternate in time, then grab their digital outputs alternately, the
effective sample rate of the signal is 120MHz.

Perhaps that's what you had in mind?  In this case, Fs would be the
frequency of each ADC, 2*Fs would be the effective sample rate of the signal
and the signal bandwidth can be up to <Fs.  So, it depends on how you define
Fs.

Or, perhaps you're thinking about sampling a bandpass signal in quadrature
in order to generate I and Q samples at baseband.  If the bandwidth is K
then the baseband extends from -K/2 to +K/2 and the sample rate is K (but
there are 2 values "per sample" because of the quadrature.  Rick Lyon's book
has a nice treatment of an efficient way of doing this as I recall.

Fred

Fred Marshall wrote:
> Vladim wrote:
> > I remember reading some time ago an article explaingng a technique using 2
> > ADCs fed with the same signal to and each runnig at
> > Fs - sampling frequency to digitize a signal  with frequencies from 0 up
>  to
> > Fs (and not up to Fs/2)

...

> Let's say you wanted to sample a signal at 120MHz and the ADCs are only good
> to 80MHz.
> If you put the same input into both the ADCs as you've mentioned, then clock
> the ADCs at 60MHz, and 180 degrees out of phase, so that their samples
> alternate in time, then grab their digital outputs alternately, the
> effective sample rate of the signal is 120MHz.

Fred, what about aliasing? Won't the signal come out completely
garbbled?

I would proceed as follows:

1. Analogue lowpass filter the signal at Fs/2 (Fs being the sampling
rate of the ADCs) and feed that to ADC1.

2. Analogue highpass filter the same signal at Fs/2 and feed that into
ADC2.

3. Take signal 2 and zero pad upsample by a factor of two, creating an
imaged version at new sampling rate 2 Fs. Now use a digital highpass
filter at Fs to filter out the original signal, just keeping the
image.

4. Zero pad upsample signal 1 by factor two. Use a digital lowpass
filter at Fs to filter out the image.

5. Add the two signals together. You then have a signal at 2 Fs with
bandwidth Fs and _no_ aliasing.

Regards,
Andor

> > Let's say you wanted to sample a signal at 120MHz and the ADCs are only
good
> > to 80MHz.
> > If you put the same input into both the ADCs as you've mentioned, then
clock
> > the ADCs at 60MHz, and 180 degrees out of phase, so that their samples
> > alternate in time, then grab their digital outputs alternately, the
> > effective sample rate of the signal is 120MHz.
>
> Fred, what about aliasing? Won't the signal come out completely
> garbbled?
>
> I would proceed as follows:
>
> 1. Analogue lowpass filter the signal at Fs/2 (Fs being the sampling
> rate of the ADCs) and feed that to ADC1.
>
> 2. Analogue highpass filter the same signal at Fs/2 and feed that into
> ADC2.
>
> 3. Take signal 2 and zero pad upsample by a factor of two, creating an
> imaged version at new sampling rate 2 Fs. Now use a digital highpass
> filter at Fs to filter out the original signal, just keeping the
> image.
>
> 4. Zero pad upsample signal 1 by factor two. Use a digital lowpass
> filter at Fs to filter out the image.
>
> 5. Add the two signals together. You then have a signal at 2 Fs with
> bandwidth Fs and _no_ aliasing.

I gotta say that fred's way is better... and works.

If you sample each ADC at 60MHz but have a 180phase difference between the
two ADC's, then you have an equivalent 120MHz sample rate.  Cause you're
getting two samples per 1/60MHz period.
As long as no samples are thrown away then you will have meaningful samples
up to the ADC frequency, which is not actually the combined sampling
frequency, that is still 2x the highest intelligible frequency in the
desired signal.

Andor wrote:
> 
> Fred Marshall wrote:

> > Let's say you wanted to sample a signal at 120MHz and the ADCs are only good
> > to 80MHz.

> > If you put the same input into both the ADCs as you've mentioned, then clock
> > the ADCs at 60MHz, and 180 degrees out of phase, so that their samples
> > alternate in time, then grab their digital outputs alternately, the
> > effective sample rate of the signal is 120MHz.
> 
> Fred, what about aliasing? Won't the signal come out completely
> garbbled?

The individual components will be aliased but the sum won't. This
is similar to the aliasing cancellation that occurs in a QMF.
Look at Fred's example as a trivial QMF with synthesis filters 1
and z^(-1).

Glenn Zelniker

"Andor" <an2or@mailcircuit.com> wrote in message
news:ce45f9ed.0312300304.548d095b@posting.google.com...
> Fred Marshall wrote:
> > Vladim wrote:
> > > I remember reading some time ago an article explaingng a technique
using 2
> > > ADCs fed with the same signal to and each runnig at
> > > Fs - sampling frequency to digitize a signal  with frequencies from 0
up
> >  to
> > > Fs (and not up to Fs/2)
>
> ...
>
> > Let's say you wanted to sample a signal at 120MHz and the ADCs are only
good
> > to 80MHz.
> > If you put the same input into both the ADCs as you've mentioned, then
clock
> > the ADCs at 60MHz, and 180 degrees out of phase, so that their samples
> > alternate in time, then grab their digital outputs alternately, the
> > effective sample rate of the signal is 120MHz.
>
> Fred, what about aliasing? Won't the signal come out completely
> garbbled?

No.  It's just a simple hardware trick to *directly* get 120MHz sample rate.
The 180 phase difference should be really easy to get in the clock
generator.  So, all you need worry about is the phase jitter as always.

Fred

"Andor" <an2or@mailcircuit.com> wrote in message
news:ce45f9ed.0312300304.548d095b@posting.google.com...
> Fred Marshall wrote:
> > Vladim wrote:
> > > I remember reading some time ago an article explaingng a technique
using 2
> > > ADCs fed with the same signal to and each runnig at
> > > Fs - sampling frequency to digitize a signal  with frequencies from 0
up
> >  to
> > > Fs (and not up to Fs/2)
>
> ...
>
> > Let's say you wanted to sample a signal at 120MHz and the ADCs are only
good
> > to 80MHz.
> > If you put the same input into both the ADCs as you've mentioned, then
clock
> > the ADCs at 60MHz, and 180 degrees out of phase, so that their samples
> > alternate in time, then grab their digital outputs alternately, the
> > effective sample rate of the signal is 120MHz.
>
> Fred, what about aliasing? Won't the signal come out completely
> garbbled?

I should have addressed the question more directly:

A:  There's no aliasing or garbling at all.  Think of this as a black box
that samples at 120Mhz.  No aliasing in the samples that come out.  How we
got them isn't important.  The input signal must not have content at 60Mhz
or above to avoid aliasing and that was the going in assumption.  In
practice, the input signal shouldn't have content above 50Mhz to allow for a
transition band.  We focused on the desired sample rate of 120Mhz earlier -
so this point about signal bandwidth needed to be made just to be clear.

Fred

"Fred Marshall" <fmarshallx@remove_the_x.acm.org> wrote in
news:TsKdnVTCFKoZKmyiRVn-hA@centurytel.net: 

> 
> "Andor" <an2or@mailcircuit.com> wrote in message
> news:ce45f9ed.0312300304.548d095b@posting.google.com...
>> Fred Marshall wrote:
>> > Vladim wrote:
>> > > I remember reading some time ago an article explaingng a
>> > > technique 
> using 2
>> > > ADCs fed with the same signal to and each runnig at
>> > > Fs - sampling frequency to digitize a signal  with frequencies
>> > > from 0 
> up
>> >  to
>> > > Fs (and not up to Fs/2)
>>
>> ...
>>
>> > Let's say you wanted to sample a signal at 120MHz and the ADCs are
>> > only 
> good
>> > to 80MHz.
>> > If you put the same input into both the ADCs as you've mentioned,
>> > then 
> clock
>> > the ADCs at 60MHz, and 180 degrees out of phase, so that their
>> > samples alternate in time, then grab their digital outputs
>> > alternately, the effective sample rate of the signal is 120MHz.
>>
>> Fred, what about aliasing? Won't the signal come out completely
>> garbbled?
> 
> No.  It's just a simple hardware trick to *directly* get 120MHz sample
> rate. The 180 phase difference should be really easy to get in the
> clock generator.  So, all you need worry about is the phase jitter as
> always. 
> 
> Fred
> 
> 

There are a couple of potential gotchas with this method. 

First you are assuming that both converters are identical. Chances are 
your conversions will not be monotonic even if each individual converter 
is. This may still be acceptable, but something to think about. You 
certainly will want to share the same voltage reference for each 
converter.

You also require that the sample and hold function of each converter is 
fast enough for the composite 120 MHz sample rate.


-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com

Al Clark wrote:
> 
> There are a couple of potential gotchas with this method.
> 
> First you are assuming that both converters are identical. Chances are
> your conversions will not be monotonic even if each individual converter
> is. This may still be acceptable, but something to think about. You
> certainly will want to share the same voltage reference for each
> converter.
> 
> You also require that the sample and hold function of each converter is
> fast enough for the composite 120 MHz sample rate.

So now you want to bring *practical* issues into this
discussion?  ;-)

Excellent points, though. And what about jitter? (And this raises
an interesting thought experiment: if the first converter is
driven by a clock with jitter j1(t), is there a jitter
characteristic j2(t) for the second clock to minimize the effect
of the jitter?)

Glenn Zelniker

Glenn Zelniker <glennz@z-sys.com> wrote in news:3FF1CDE8.24DD986A@z-
sys.com:

> Al Clark wrote:
>> 
>> There are a couple of potential gotchas with this method.
>> 
>> First you are assuming that both converters are identical. Chances are
>> your conversions will not be monotonic even if each individual 
converter
>> is. This may still be acceptable, but something to think about. You
>> certainly will want to share the same voltage reference for each
>> converter.
>> 
>> You also require that the sample and hold function of each converter 
is
>> fast enough for the composite 120 MHz sample rate.
> 
> So now you want to bring *practical* issues into this
> discussion?  ;-)

Well, someone has gotta build hardware......

> 
> Excellent points, though. And what about jitter? (And this raises
> an interesting thought experiment: if the first converter is
> driven by a clock with jitter j1(t), is there a jitter
> characteristic j2(t) for the second clock to minimize the effect
> of the jitter?)
> 
> Glenn Zelniker
> 

Clock jitter can be a problem with any converter. With a two converter 
architecture, its probably messier. I don't think the second converter 
can do anything to help the situation.

There is another problem that is clock related. You have to make sure 
that each converter samples at exactly half intervals. For example, You 
don't want to use a falling edge of the first converter's clock with an 
inverter for the second clock because the delays will kill you. You 
probably could use a divide by 2 counter and drive the converters from 
the Q and !Q outputs of the flip-flop. 

The good news is that by the time you make your two converter circuit 
work, the chip manufacturers will have a part that is twice as fast.

-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com