Using 2 ADCs

"Fred Marshall" <fmarshallx@remove_the_x.acm.org> wrote in message news:<LfudnYmzJI5_JWyiRVn-iw@centurytel.net>...
> "Andor" <an2or@mailcircuit.com> wrote in message
> news:ce45f9ed.0312300304.548d095b@posting.google.com...
> > Fred Marshall wrote:
> > > Vladim wrote:
> > > > I remember reading some time ago an article explaingng a technique
>  using 2
> > > > ADCs fed with the same signal to and each runnig at
> > > > Fs - sampling frequency to digitize a signal  with frequencies from 0
>  up
>  to
> > > > Fs (and not up to Fs/2)
> >
> > ...
> >
> > > Let's say you wanted to sample a signal at 120MHz and the ADCs are only
>  good
> > > to 80MHz.
> > > If you put the same input into both the ADCs as you've mentioned, then
>  clock
> > > the ADCs at 60MHz, and 180 degrees out of phase, so that their samples
> > > alternate in time, then grab their digital outputs alternately, the
> > > effective sample rate of the signal is 120MHz.
> >
> > Fred, what about aliasing? Won't the signal come out completely
> > garbbled?
> 
> I should have addressed the question more directly:
> 
> A:  There's no aliasing or garbling at all.  Think of this as a black box
> that samples at 120Mhz.  No aliasing in the samples that come out.  How we
> got them isn't important.  The input signal must not have content at 60Mhz
> or above to avoid aliasing and that was the going in assumption.  In
> practice, the input signal shouldn't have content above 50Mhz to allow for a
> transition band.  We focused on the desired sample rate of 120Mhz earlier -
> so this point about signal bandwidth needed to be made just to be clear.
> 
> Fred


Another practical issue; the propagation delay between when the clock
signal arrives at the clock pin of the converter chip, and when the
input actually gets sampled. This will vary between parts, and at high
speeds it will matter a lot. Ditto for gain errors. Also, two seperate
ICs will not track over time/temp etc. This is not just a minor issue;
if you want the aliases to cancel on the order of 80 dB, you need gain
errors between the two seperate IC's of less than 1 part in 10000,
which is pretty tough (200uv on a 2-volt reference). The sampling-time
errors could be even worse, especially for large high-frequency
signals.

This type of scheme must usually have an auto-calibration algorithm to
go along with it. Even better, and auto-calibration scheme that works
all the time in the background. Many schemes already exist for this,
but are best implemented in hardware on the chip itself.

Bob Adams

"Fred Marshall" <fmarshallx@remove_the_x.acm.org> wrote in message news:<DMednd3RVsDxuWyi4p2dnA@centurytel.net>...
> "Vadim Lebedev" <vadiml@libertysurf.fr> wrote in message
> news:bsqpcc$b3k$1@news.tiscali.fr...
> > Hello,
> >
> > I remember reading some time ago an article explaingng a technique using 2
> > ADCs fed with the same signal to and each runnig at
> > Fs - sampling frequency to digitize a signal  with frequencies from 0 up
>  to
> > Fs (and not up to Fs/2)
> >
> >
> > I'm unable to find this article again.
> >
> > Can  somebody please, explain me the technique or point me to a text
> > explaning it?
> 
> Vadim,
> 
> Well, it has been rather common practice to use 2 ADCs when the maximum
> sample rate capability of the ADCs was lower than the needed sample rate for
> the signal.
> Let's say you wanted to sample a signal at 120MHz and the ADCs are only good
> to 80MHz.
> If you put the same input into both the ADCs as you've mentioned, then clock
> the ADCs at 60MHz, and 180 degrees out of phase, so that their samples
> alternate in time, then grab their digital outputs alternately, the
> effective sample rate of the signal is 120MHz.
> 
> Perhaps that's what you had in mind?  In this case, Fs would be the
> frequency of each ADC, 2*Fs would be the effective sample rate of the signal
> and the signal bandwidth can be up to <Fs.  So, it depends on how you define
> Fs.
> 
> Or, perhaps you're thinking about sampling a bandpass signal in quadrature
> in order to generate I and Q samples at baseband.  If the bandwidth is K
> then the baseband extends from -K/2 to +K/2 and the sample rate is K (but
> there are 2 values "per sample" because of the quadrature.  Rick Lyon's book
> has a nice treatment of an efficient way of doing this as I recall.
> 
> Fred

What good ways can I think of for the true masochist to spend their
time:

- Self flagellation

- Subservience to a sadist

- Trying to get all the element ADCs in a poly-phase ADC to track well
enough over time and temperature. Throw in trying to get the clocks
aligned well enough, when the even the delay between the clock input
pin of each converter and the converter core varies a little. Add the
tighter sampling aperture jitter requirements. Oh, there's excellent
potential here for lots of long term pain and misery.

Been there. Suffered that! :-)

Regards,
Steve

On 30 Dec 2003 20:25:58 -0800, steveu@coppice.org (Steve Underwood)
wrote:

>
>- Trying to get all the element ADCs in a poly-phase ADC to track well
>enough over time and temperature. Throw in trying to get the clocks
>aligned well enough, when the even the delay between the clock input
>pin of each converter and the converter core varies a little. Add the
>tighter sampling aperture jitter requirements. Oh, there's excellent
>potential here for lots of long term pain and misery.

This isn't so bad if all the ADCs are on the same die.  I recall an
Agilent ADC designed for oscilloscope use that could sample at 8GHz
(real time) in 0.35um CMOS.  I think it might have had sixteen ADCs.

Regards,
Allan.

Glenn Zelniker wrote:
> Andor wrote:
> > 
> > Fred Marshall wrote:
>  
> > > Let's say you wanted to sample a signal at 120MHz and the ADCs are only good
> > > to 80MHz.
>  
> > > If you put the same input into both the ADCs as you've mentioned, then clock
> > > the ADCs at 60MHz, and 180 degrees out of phase, so that their samples
> > > alternate in time, then grab their digital outputs alternately, the
> > > effective sample rate of the signal is 120MHz.
> > 
> > Fred, what about aliasing? Won't the signal come out completely
> > garbbled?
> 
> The individual components will be aliased but the sum won't. This
> is similar to the aliasing cancellation that occurs in a QMF.
> Look at Fred's example as a trivial QMF with synthesis filters 1
> and z^(-1).

I get it. When looking at it in time domain, this method seems to work
quite naturally. I had problems when I looked in frequency domain,
where I saw aliases all over the place :). But due to the phase shift
of 180� in sampling, the aliases are also wideband shifted by 180�.
Thus adding them up cancels the aliases and just leaves the images
(which were created when we implicitely upsampled to add the two
signals together).

As you write, it is similar to polyphase filtering - I guess you could
call it polyphase sampling. It also works for any k-fold sampling
frequency by using k ADCs. The phase shift affected on the aliases
will be 360�/k, and that their sum equals to zero can be explained by
the fact that the k unity roots add up to zero.

This is indeed a lot simpler than what I proposed!

Glenn, in another post you mentioned the processing power of the
TigerSHARCS - could it be that you are changing to the ADI camp? Did
you also see their new audio-specific DSP series 212xx and 213xx? You
can download this for a quick overview:

http://www.analog.com/UploadedFiles/Product_Highlights/2997787805749303-AND-088_SharcAudio4.pdf

I find it ridiculous that ADI made the TigerSHARCs without serial
ports - every DSP should have serial ports! The problem with the 212xx
and 213xx is that they are not intended for multi-processing, ie. no
link ports. Also a pity <sigh>.

Happy new year to everybody!

Regards,
Andor

> 
> Glenn Zelniker

Is this Andor at Weiss Engineering? If so, hello and best
regards. If not, well... hello and best regards also. 

Andor wrote:
> 
> Glenn, in another post you mentioned the processing power of the
> TigerSHARCS - could it be that you are changing to the ADI camp? Did
> you also see their new audio-specific DSP series 212xx and 213xx? You
> can download this for a quick overview:
 
[snip]

Yes, the ADI guy at AES NYC told me about this. It looks good. I
am indeed contemplating a move to the ADI camp, having just about
exhausted what I can do with the TI family. 192 kHz, 384 kHz, and
DSD have finally forced my hand! The immediate short term,
however, has me doing native DSP on the PPC970 (i.e., Apple G5),
so I won't be doing anything with ADI for a while. BTW, the G5 is
quite impressive as a DSP.
 
> I find it ridiculous that ADI made the TigerSHARCs without serial
> ports - every DSP should have serial ports! The problem with the 212xx
> and 213xx is that they are not intended for multi-processing, ie. no
> link ports. Also a pity <sigh>.

Indeed. One has to wonder sometimes if the chip-design groups
include anybody who has ever worked in end-product development.
 
> Happy new year to everybody!

Likewise. And hello and best regards to Daniel if this is the
Andor I have in mind.

Glenn

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<e5m4vvcojn2c10q1qqm3sbp8503kkot71m@4ax.com>...
> This isn't so bad if all the ADCs are on the same die.  I recall an
> Agilent ADC designed for oscilloscope use that could sample at 8GHz
> (real time) in 0.35um CMOS.  I think it might have had sixteen ADCs.

Sounds an interesting device. However, scopes are not that demanding
of conversion quality. Many scopes only use 6 bit converters. The
screen doesn't really have a great deal of resolution. The need a
pretty darn snappy sampler at that rate, though :-)

Regards,
Steve

steveu@coppice.org (Steve Underwood) wrote in message news:<80bddbd7.0312302025.385e59f2@posting.google.com>...
> "Fred Marshall" <fmarshallx@remove_the_x.acm.org> wrote in message news:<DMednd3RVsDxuWyi4p2dnA@centurytel.net>...
> > "Vadim Lebedev" <vadiml@libertysurf.fr> wrote in message
> > news:bsqpcc$b3k$1@news.tiscali.fr...
> > > Hello,
> > >
> > > I remember reading some time ago an article explaingng a technique using 2
> > > ADCs fed with the same signal to and each runnig at
> > > Fs - sampling frequency to digitize a signal  with frequencies from 0 up
>  to
> > > Fs (and not up to Fs/2)
> > >
> > >
> > > I'm unable to find this article again.
> > >
> > > Can  somebody please, explain me the technique or point me to a text
> > > explaning it?
> > 
> > Vadim,
> > 
> > Well, it has been rather common practice to use 2 ADCs when the maximum
> > sample rate capability of the ADCs was lower than the needed sample rate for
> > the signal.
> > Let's say you wanted to sample a signal at 120MHz and the ADCs are only good
> > to 80MHz.
> > If you put the same input into both the ADCs as you've mentioned, then clock
> > the ADCs at 60MHz, and 180 degrees out of phase, so that their samples
> > alternate in time, then grab their digital outputs alternately, the
> > effective sample rate of the signal is 120MHz.
> > 
> > Perhaps that's what you had in mind?  In this case, Fs would be the
> > frequency of each ADC, 2*Fs would be the effective sample rate of the signal
> > and the signal bandwidth can be up to <Fs.  So, it depends on how you define
> > Fs.
> > 
> > Or, perhaps you're thinking about sampling a bandpass signal in quadrature
> > in order to generate I and Q samples at baseband.  If the bandwidth is K
> > then the baseband extends from -K/2 to +K/2 and the sample rate is K (but
> > there are 2 values "per sample" because of the quadrature.  Rick Lyon's book
> > has a nice treatment of an efficient way of doing this as I recall.
> > 
> > Fred
> 
> What good ways can I think of for the true masochist to spend their
> time:
> 
> - Self flagellation
> 
> - Subservience to a sadist
> 
> - Trying to get all the element ADCs in a poly-phase ADC to track well
> enough over time and temperature. Throw in trying to get the clocks
> aligned well enough, when the even the delay between the clock input
> pin of each converter and the converter core varies a little. Add the
> tighter sampling aperture jitter requirements. Oh, there's excellent
> potential here for lots of long term pain and misery.
> 
> Been there. Suffered that! :-)
> 
> Regards,
> Steve

Well Steve,

Actually i was planning to use a PIC or AVR  MCUs wit thier builtin ADCs so
i beilieve there will be no special clock jitter considerations 

Vadim

Glenn Zelniker wrote:
> Is this Andor at Weiss Engineering? 
Yes.

>If so, hello and best
> regards. If not, well... hello and best regards also. 

Well, hello there too. Good you could join us here :).


> The immediate short term,
> however, has me doing native DSP on the PPC970 (i.e., Apple G5),
> so I won't be doing anything with ADI for a while. BTW, the G5 is
> quite impressive as a DSP.

I can imagine, it sure has the number crunching power. 

  
> Likewise. And hello and best regards to Daniel if this is the
> Andor I have in mind.

I'll relay it to him.

Regards,
Andor

Al Clark wrote:

(snip)

>>>>the ADCs at 60MHz, and 180 degrees out of phase, so that their
>>>>samples alternate in time, then grab their digital outputs
>>>>alternately, the effective sample rate of the signal is 120MHz.

(snip)

> There are a couple of potential gotchas with this method. 

> First you are assuming that both converters are identical. Chances are 
> your conversions will not be monotonic even if each individual converter 
> is. This may still be acceptable, but something to think about. You 
> certainly will want to share the same voltage reference for each 
> converter.

It would seem to me that this would add noise at Fs/2.  That could
be filtered out in the digital signal.

> You also require that the sample and hold function of each converter is 
> fast enough for the composite 120 MHz sample rate.

This is always a problem for any converter.  Ideally, the sample width
should be 0, but never is.

-- glen

Andor wrote:

(snip)

> I get it. When looking at it in time domain, this method seems to work
> quite naturally. I had problems when I looked in frequency domain,
> where I saw aliases all over the place :). But due to the phase shift
> of 180� in sampling, the aliases are also wideband shifted by 180�.
> Thus adding them up cancels the aliases and just leaves the images
> (which were created when we implicitely upsampled to add the two
> signals together).

There was a design I saw some years ago, where someone wanted a fast
8 bit A/D and only four bit ones were available that fast.   They
did something like A/D with four bits, D/A the result.  Analog subtract
from the original signal, A/D the difference.   The A/D must be
linear enough to do it right, but only take the time of a four bit A/D.

-- glen