On Thu, 08 Jan 2004 00:51:55 GMT, glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:>Andor wrote: > >(snip) > >> I get it. When looking at it in time domain, this method seems to work >> quite naturally. I had problems when I looked in frequency domain, >> where I saw aliases all over the place :). But due to the phase shift >> of 180� in sampling, the aliases are also wideband shifted by 180�. >> Thus adding them up cancels the aliases and just leaves the images >> (which were created when we implicitely upsampled to add the two >> signals together). > >There was a design I saw some years ago, where someone wanted a fast >8 bit A/D and only four bit ones were available that fast. They >did something like A/D with four bits, D/A the result. Analog subtract >from the original signal, A/D the difference. The A/D must be >linear enough to do it right, but only take the time of a four bit A/D.I believe that almost all high speed, high resolution ADCs work this way. Any ADC that's described as "pipelined" will have multiple lower resolution ADC and DAC pairs. [ This shouldn't be confused with a Flash converter with a pipeline register on the output! Flash converters have a size that grows exponentially with the number of bits in the result; this limits them to about 9 or 10 bits. ] ADCs don't need to be particularly high speed to use this technique. For example, the MAX1200 is a 16 bit, 1 Msps converter that uses 4 pipelined ADC/DAC stages. http://pdfserv.maxim-ic.com/en/ds/MAX1200.pdf Oh, the first DAC needs to be accurate to the full precision of the ADC. The individual ADCs in the pipeline can have a lower precision (and accuracy). Regards, Allan.
Using 2 ADCs
Started by ●December 29, 2003
Reply by ●January 7, 20042004-01-07
