i've included a link where i've stored the costas loop model i've been work= ing on. I am sorry, i am new here, and i did try to search and get a hold o= f as many literature on the topic as possible. http://dl.dropbox.com/u/102875916/COSTAS_PI_4_PROBLEM.mdl my loop bW is: 1KHz my Sampling: 100 MHz Symbol Rate: 1Mhz arm filter cutoffs: .5MHz -> 9MHz (both FIRs) Loop Filters: values derived from Dr. Rice's book equations I am not sure I have implemented it correctly. The loop seems to track ok (= I've tried it with modulated data and it works ok) whenever the phase offse= t i apply is a non a PI/4 term. at PI/4, 3PI/4, 6PI/4, and so forth, it's i= n no-man's land. I think that's what's called a cycle slip???.=20 -while at it, i want to know how to detect when there's slippage and engage= the loop per se, or what's the mechanism for the state detection algorithm= ? i just want to know that I am at least in the right direction. Please, some= one kindly has looked over my simulink model, tell me where I am going wron= g with the design. (i've worked on this for about a month non-stop now, and= I don't know if i can read or study anything more to make me have an epiph= any alone). P.S. i did look at the model built posted at a russian website. It makes se= nse except that it's all done at a baseband processing. I've questions abou= t that too but that maybe later. thanks and (great community by the way) sam
Costas loop problem at a specific phase angle
Started by ●September 11, 2012
Reply by ●September 11, 20122012-09-11
On Tue, 11 Sep 2012 18:11:45 -0700, samberhanu wrote:> i've included a link where i've stored the costas loop model i've been > working on. I am sorry, i am new here, and i did try to search and get a > hold of as many literature on the topic as possible. > > http://dl.dropbox.com/u/102875916/COSTAS_PI_4_PROBLEM.mdl > > my loop bW is: 1KHz my Sampling: 100 MHz Symbol Rate: 1Mhz arm filter > cutoffs: .5MHz -> 9MHz (both FIRs) > > Loop Filters: values derived from Dr. Rice's book equations > > I am not sure I have implemented it correctly. The loop seems to track > ok (I've tried it with modulated data and it works ok) whenever the > phase offset i apply is a non a PI/4 term. at PI/4, 3PI/4, 6PI/4, and so > forth, it's in no-man's land. I think that's what's called a cycle > slip???. > > -while at it, i want to know how to detect when there's slippage and > engage the loop per se, or what's the mechanism for the state detection > algorithm? > > i just want to know that I am at least in the right direction. Please, > someone kindly has looked over my simulink model, tell me where I am > going wrong with the design. (i've worked on this for about a month > non-stop now, and I don't know if i can read or study anything more to > make me have an epiphany alone). > > P.S. i did look at the model built posted at a russian website. It makes > sense except that it's all done at a baseband processing. I've questions > about that too but that maybe later. > thanks and (great community by the way) > > samFew of us have Simulink. Surprisingly enough, DSP does not equal Matlab, and facility with one does not necessarily follow from facility with the other. Perhaps if you gave us a succinct mathematical model of the loop we could help you out -- you'll find that there's not a lot of enthusiasm in this group for blindly trusting to math packages: that's not generally the route to understanding in DSP problems. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
Reply by ●September 12, 20122012-09-12
On 9/11/2012 6:11 PM, samberhanu@gmail.com wrote:> I am not sure I have implemented it correctly. The loop seems to track > ok (I've tried it with modulated data and it works ok) whenever the> phase offset i apply is a non a PI/4 term. at PI/4, 3PI/4, 6PI/4, > and so forth, it's in no-man's land. I think that's what's called > a cycle slip???. If I recall correctly, the Costas loop can "lock" at either of two phases with respect to the carrier: 0 degrees and 180 degrees. Is that what you are seeing? Rob
Reply by ●September 12, 20122012-09-12
On Sep 12, 12:22�am, Rob Doyle <radioe...@gmail.com> wrote:> On 9/11/2012 6:11 PM, samberh...@gmail.com wrote:> I am not sure I have implemented it correctly. The loop seems to track > > ok (I've tried it with modulated data and it works ok) whenever the > > �> phase offset i apply is a non a PI/4 term. at PI/4, 3PI/4, 6PI/4, > �> and so forth, it's in no-man's land. I think that's what's called > �> a cycle slip???. > > If I recall correctly, the Costas loop can "lock" at either of two > phases with respect to the carrier: 0 degrees and 180 degrees. > > Is that what you are seeing? > > Robthere's a name I know... Hi Bob! Mark
Reply by ●September 12, 20122012-09-12
On Tue, 11 Sep 2012 21:21:57 -0700, Rob Doyle wrote:> On 9/11/2012 6:11 PM, samberhanu@gmail.com wrote: >> I am not sure I have implemented it correctly. The loop seems to track >> ok (I've tried it with modulated data and it works ok) whenever the > > phase offset i apply is a non a PI/4 term. at PI/4, 3PI/4, 6PI/4, and > > so forth, it's in no-man's land. I think that's what's called a cycle > > slip???. > > If I recall correctly, the Costas loop can "lock" at either of two > phases with respect to the carrier: 0 degrees and 180 degrees. > > Is that what you are seeing?If it's a properly implemented Costas loop and it's quadrature PSK, then it'll lock at 0, 90, 180 and -90. -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.com
Reply by ●September 13, 20122012-09-13
On Wednesday, September 12, 2012 5:43:36 PM UTC-4, Tim Wescott wrote:> On Tue, 11 Sep 2012 21:21:57 -0700, Rob Doyle wrote: > > > > > On 9/11/2012 6:11 PM, samberhanu@gmail.com wrote: > > >> I am not sure I have implemented it correctly. The loop seems to track > > >> ok (I've tried it with modulated data and it works ok) whenever the > > > > phase offset i apply is a non a PI/4 term. at PI/4, 3PI/4, 6PI/4, and > > > > so forth, it's in no-man's land. I think that's what's called a cycle > > > > slip???. > > > > > > If I recall correctly, the Costas loop can "lock" at either of two > > > phases with respect to the carrier: 0 degrees and 180 degrees. > > > > > > Is that what you are seeing? > > > > If it's a properly implemented Costas loop and it's quadrature PSK, then > > it'll lock at 0, 90, 180 and -90. > > > > > > -- > > My liberal friends think I'm a conservative kook. > > My conservative friends think I'm a liberal kook. > > Why am I not happy that they have found common ground? > > > > Tim Wescott, Communications, Control, Circuits & Software > > http://www.wescottdesign.comthanks for your input. this is a BPSK signal. It locks at 0 & 180 as expected. But i've found out that my loop does this at the expense of a non-zero stead-state error. I guess that means it's really not correctly locking. Is this the phenomenon called false lock? How can i improve the steady state error? it's a positive steady state error. as far as i remember from control theory, this is done by increasing the proportional controller (Mr. Wescott, your article infers this also) one of the most frustrating things about this is that I have to find the proportional gain for the controller. It's supposed to be the slope of the s-curve at angle zero? I think it is but even with that value it seems it's not working. the equation set in Dr. Rice's book states Kp => the proportional controller gain to be set to 1/T*AGC gain * AGC(Vpp)^2.... is that correct?
Reply by ●September 13, 20122012-09-13
On Sep 13, 7:39�pm, samb <samberh...@gmail.com> wrote:> On Wednesday, September 12, 2012 5:43:36 PM UTC-4, Tim Wescott wrote: > > On Tue, 11 Sep 2012 21:21:57 -0700, Rob Doyle wrote: > > > > On 9/11/2012 6:11 PM, samberh...@gmail.com wrote: > > > >> I am not sure I have implemented it correctly. The loop seems to track > > > >> ok (I've tried it with modulated data and it works ok) whenever the > > > > �> phase offset i apply is a non a PI/4 term. at PI/4, 3PI/4, 6PI/4, and > > > > �> so forth, it's in no-man's land. I think that's what's called a cycle > > > > �> slip???. > > > > If I recall correctly, the Costas loop can "lock" at either of two > > > > phases with respect to the carrier: 0 degrees and 180 degrees. > > > > Is that what you are seeing? > > > If it's a properly implemented Costas loop and it's quadrature PSK, then > > > it'll lock at 0, 90, 180 and -90. > > > -- > > > My liberal friends think I'm a conservative kook. > > > My conservative friends think I'm a liberal kook. > > > Why am I not happy that they have found common ground? > > > Tim Wescott, Communications, Control, Circuits & Software > > >http://www.wescottdesign.com > > thanks for your input. > this is a BPSK signal. It locks at 0 & 180 as expected. But i've found out that my loop does this at the expense of a non-zero stead-state error. I guess that means it's really not correctly locking. Is this the phenomenon called false lock? > How can i improve the steady state error? it's a positive steady state error. as far as i remember from control theory, this is done by increasing the proportional controller (Mr. Wescott, your article infers this also) > > one of the most frustrating things about this is that I have to find the proportional gain for the controller. It's supposed to be the slope of the s-curve at angle zero? I think it is but even with that value it seems it's not working. the equation set in Dr. Rice's book states Kp => the proportional controller gain to be set to 1/T*AGC gain * AGC(Vpp)^2.... is that correct?here's another book that may help http://www.amazon.com/The-Theory-Practice-Modem-Design/dp/0471851086 MJark
Reply by ●September 13, 20122012-09-13
On Thursday, September 13, 2012 8:47:30 PM UTC-4, Mark wrote:> On Sep 13, 7:39�pm, samb <samberh...@gmail.com> wrote: > > > On Wednesday, September 12, 2012 5:43:36 PM UTC-4, Tim Wescott wrote: > > > > On Tue, 11 Sep 2012 21:21:57 -0700, Rob Doyle wrote: > > > > > > > > On 9/11/2012 6:11 PM, samberh...@gmail.com wrote: > > > > > > > >> I am not sure I have implemented it correctly. The loop seems to track > > > > > > > >> ok (I've tried it with modulated data and it works ok) whenever the > > > > > > > > �> phase offset i apply is a non a PI/4 term. at PI/4, 3PI/4, 6PI/4, and > > > > > > > > �> so forth, it's in no-man's land. I think that's what's called a cycle > > > > > > > > �> slip???. > > > > > > > > If I recall correctly, the Costas loop can "lock" at either of two > > > > > > > > phases with respect to the carrier: 0 degrees and 180 degrees. > > > > > > > > Is that what you are seeing? > > > > > > > If it's a properly implemented Costas loop and it's quadrature PSK, then > > > > > > > it'll lock at 0, 90, 180 and -90. > > > > > > > -- > > > > > > > My liberal friends think I'm a conservative kook. > > > > > > > My conservative friends think I'm a liberal kook. > > > > > > > Why am I not happy that they have found common ground? > > > > > > > Tim Wescott, Communications, Control, Circuits & Software > > > > > > >http://www.wescottdesign.com > > > > > > thanks for your input. > > > this is a BPSK signal. It locks at 0 & 180 as expected. But i've found out that my loop does this at the expense of a non-zero stead-state error. I guess that means it's really not correctly locking. Is this the phenomenon called false lock? > > > How can i improve the steady state error? it's a positive steady state error. as far as i remember from control theory, this is done by increasing the proportional controller (Mr. Wescott, your article infers this also) > > > > > > one of the most frustrating things about this is that I have to find the proportional gain for the controller. It's supposed to be the slope of the s-curve at angle zero? I think it is but even with that value it seems it's not working. the equation set in Dr. Rice's book states Kp => the proportional controller gain to be set to 1/T*AGC gain * AGC(Vpp)^2.... is that correct? > > > > here's another book that may help > > > > http://www.amazon.com/The-Theory-Practice-Modem-Design/dp/0471851086 > > > > MJarkthe reviews seem to be poor. nevertheless, for ten bucks, worth taking a shot, so ordered. hopefully, it'll help.
Reply by ●September 14, 20122012-09-14
On Thu, 13 Sep 2012 16:39:17 -0700 (PDT), samb <samberhanu@gmail.com> wrote:>On Wednesday, September 12, 2012 5:43:36 PM UTC-4, Tim Wescott wrote: >> On Tue, 11 Sep 2012 21:21:57 -0700, Rob Doyle wrote: >>=20 >>=20 >>=20 >> > On 9/11/2012 6:11 PM, samberhanu@gmail.com wrote: >>=20 >> >> I am not sure I have implemented it correctly. The loop seems to track >>=20 >> >> ok (I've tried it with modulated data and it works ok) whenever the >>=20 >> > > phase offset i apply is a non a PI/4 term. at PI/4, 3PI/4, 6PI/4, an= >d >>=20 >> > > so forth, it's in no-man's land. I think that's what's called a cycl= >e >>=20 >> > > slip???. >>=20 >> >=20 >>=20 >> > If I recall correctly, the Costas loop can "lock" at either of two >>=20 >> > phases with respect to the carrier: 0 degrees and 180 degrees. >>=20 >> >=20 >>=20 >> > Is that what you are seeing? >>=20 >>=20 >>=20 >> If it's a properly implemented Costas loop and it's quadrature PSK, then= >=20 >>=20 >> it'll lock at 0, 90, 180 and -90. >>=20 >>=20 >>=20 >>=20 >>=20 >> --=20 >>=20 >> My liberal friends think I'm a conservative kook. >>=20 >> My conservative friends think I'm a liberal kook. >>=20 >> Why am I not happy that they have found common ground? >>=20 >>=20 >>=20 >> Tim Wescott, Communications, Control, Circuits & Software >>=20 >> http://www.wescottdesign.com > >thanks for your input. >this is a BPSK signal. It locks at 0 & 180 as expected. But i've found out = >that my loop does this at the expense of a non-zero stead-state error. I gu= >ess that means it's really not correctly locking. Is this the phenomenon ca= >lled false lock?=20How is this "steady state error" being measured and where? Do you mean it locks with some phase offset from 0 and 180? Do you mean the loop filter has a non-zero DC output? Do you mean it's slowly rotating? Help us out here and be clear about what you mean.>How can i improve the steady state error? it's a positive steady state erro= >r. as far as i remember from control theory, this is done by increasing the= > proportional controller (Mr. Wescott, your article infers this also)=20First you need to explain what you mean by "steady state error".>one of the most frustrating things about this is that I have to find the pr= >oportional gain for the controller. It's supposed to be the slope of the s-= >curve at angle zero? I think it is but even with that value it seems it's n= >ot working. the equation set in Dr. Rice's book states Kp =3D> the proporti= >onal controller gain to be set to 1/T*AGC gain * AGC(Vpp)^2.... is that cor= >rect?Eric Jacobsen Anchor Hill Communications www.anchorhill.com
Reply by ●September 14, 20122012-09-14
On Thu, 13 Sep 2012 16:39:17 -0700, samb wrote:> On Wednesday, September 12, 2012 5:43:36 PM UTC-4, Tim Wescott wrote: >> On Tue, 11 Sep 2012 21:21:57 -0700, Rob Doyle wrote: >> >> >> >> > On 9/11/2012 6:11 PM, samberhanu@gmail.com wrote: >> >> >> I am not sure I have implemented it correctly. The loop seems to >> >> track >> >> >> ok (I've tried it with modulated data and it works ok) whenever the >> >> > > phase offset i apply is a non a PI/4 term. at PI/4, 3PI/4, 6PI/4, >> > > and >> >> > > so forth, it's in no-man's land. I think that's what's called a >> > > cycle >> >> > > slip???. >> >> >> > >> > If I recall correctly, the Costas loop can "lock" at either of two >> >> > phases with respect to the carrier: 0 degrees and 180 degrees. >> >> >> > >> > Is that what you are seeing? >> >> >> >> If it's a properly implemented Costas loop and it's quadrature PSK, >> then >> >> it'll lock at 0, 90, 180 and -90. >> >> >> >> >> >> -- >> >> My liberal friends think I'm a conservative kook. >> >> My conservative friends think I'm a liberal kook. >> >> Why am I not happy that they have found common ground? >> >> >> >> Tim Wescott, Communications, Control, Circuits & Software >> >> http://www.wescottdesign.com > > thanks for your input. > this is a BPSK signal. It locks at 0 & 180 as expected. But i've found > out that my loop does this at the expense of a non-zero stead-state > error. I guess that means it's really not correctly locking. Is this the > phenomenon called false lock?False lock happens when there's a glitch in the phase detector response that makes the thing lock at the wrong place, or (depending on who's defining the term) when the loop manages to get balanced at a point where the phase detector slope is zero, but the loop is unstable.> How can i improve the steady state error? > it's a positive steady state error. as far as i remember from control > theory, this is done by increasing the proportional controller (Mr. > Wescott, your article infers this also)The way to eliminate steady-state error, assuming that your phase detector is working correctly, is with an integrator in the controller. Proportional gain will reduce, but never eliminate, steady-state error. If your phase detector isn't putting out zero at zero error, then you have bigger problems than your gain setting.> one of the most frustrating things about this is that I have to find the > proportional gain for the controller. It's supposed to be the slope of > the s-curve at angle zero? I think it is but even with that value it > seems it's not working. the equation set in Dr. Rice's book states Kp => > the proportional controller gain to be set to 1/T*AGC gain * > AGC(Vpp)^2.... is that correct?AGC? Automatic Gain Control? Where did that come in? The gain of the phase detector is the slope of the phase detection characteristic around zero error -- but that's data dependent, because there's only information when the data changes from 0 to 1 or visa- versa. So a long string of ones or zeros means you have no gain, while a long string of 0-1-0-1 means the gain is maximum -- you need to design your loop with this randomly varying gain in mind, or you need to design your transmission protocol to insure plenty of transitions. -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.com
