Hi sampling gurus, I'm thinking about undersampling a 150Hz AM signal modulated to a 330MHz carrier, thus the signal bandwidth is 300Hz. I found an ADC has 600MHz analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the bandpass filter is sharp enough for my my signal at 330MHz, if I use 5kHz to sample the 330MHz, will there be any problem? One of my colleagues thinks there's a sinc roll-off associates with undersampling thus one cannot use very large undersampling factor. This is true for stealing higher harmonics out of a low Fs driven DAC, but I don't think this is true for ADC. As I understand, the ADC can be modeled as: 1. Sampling: multiply input continuous signal with a series of Diract implues 2. Hold： time domain convolution with a rect window, whose width is maximally Ts (and whose freq domain is a sinc, with first null at Fs) 3. A-to-D: convert the held stable voltage to digital output using proper coding The aliasing effect due to undersampling happens in the 1st step, thus the 330MHz has already been "down-converted" to baseband to 601.2Hz, and my two AM bands will be at 451.2 and 751.2 respectively. Then the hold operation simply "mask" the frequency spectrum by a sinc shape and my 601.2Hz signal will be almost intact. Thus I won't need to do large factor decimation/filtering and save a lot of FPGA resources. Is this practically feasible? I asked a couple of engineers and they are not very sure..

# Is it possible to use very large undersampling factor (using 5.1kHz to sample 330MHz)?

Started by ●September 23, 2012

Reply by ●September 23, 20122012-09-23

On 9/23/2012 5:15 PM, nick cake wrote:> Hi sampling gurus, > > I'm thinking about undersampling a 150Hz AM signal modulated to a 330MHz carrier, thus the signal bandwidth is 300Hz. I found an ADC has 600MHz analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the bandpass filter is sharp enough for my my signal at 330MHz, if I use 5kHz to sample the 330MHz, will there be any problem? > > One of my colleagues thinks there's a sinc roll-off associates with undersampling thus one cannot use very large undersampling factor. This is true for stealing higher harmonics out of a low Fs driven DAC, but I don't think this is true for ADC. > > As I understand, the ADC can be modeled as: > 1. Sampling: multiply input continuous signal with a series of Diract implues > 2. Hold： time domain convolution with a rect window, whose width is maximally Ts (and whose freq domain is a sinc, with first null at Fs) > 3. A-to-D: convert the held stable voltage to digital output using proper coding > > The aliasing effect due to undersampling happens in the 1st step, thus the 330MHz has already been "down-converted" to baseband to 601.2Hz, and my two AM bands will be at 451.2 and 751.2 respectively. Then the hold operation simply "mask" the frequency spectrum by a sinc shape and my 601.2Hz signal will be almost intact. > > Thus I won't need to do large factor decimation/filtering and save a lot of FPGA resources. > > Is this practically feasible? I asked a couple of engineers and they are not very sure..Consider the difference between your analysis and this... Sample by flash converter at 1 GHz so that your carrier is well below the Nyquist rate. Then you drop 199,999 out of 200,000 samples to get a 5 kHz sample rate. How is this different from what you have described (assuming I did the ratio right :-)? Rick

Reply by ●September 23, 20122012-09-23

nick cake <nickcake@gmail.com> writes:> Hi sampling gurus, > > I'm thinking about undersampling a 150Hz AM signal modulated to a > 330MHz carrier, thus the signal bandwidth is 300Hz. I found an ADC has > 600MHz analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the > bandpass filter is sharp enough for my my signal at 330MHz, if I use > 5kHz to sample the 330MHz, will there be any problem? > > One of my colleagues thinks there's a sinc roll-off associates with > undersampling thus one cannot use very large undersampling factor. > This is true for stealing higher harmonics out of a low Fs driven DAC, > but I don't think this is true for ADC.Hey Nick, Sinc roll-off was associated with oversampling DACs in the old days (circa late 80s or earlier?) since those would upsample by simply replicating samples (instead of performing a polyphase lowpass filter). This creates the sinc distortion your colleague may have been thinking of.> As I understand, the ADC can be modeled as: > 1. Sampling: multiply input continuous signal with a series of Diract implues > 2. Hold： time domain convolution with a rect window, whose width is maximally Ts (and whose freq domain is a sinc, with first null at Fs) > 3. A-to-D: convert the held stable voltage to digital output using proper coding > > The aliasing effect due to undersampling happens in the 1st step, thus > the 330MHz has already been "down-converted" to baseband to 601.2Hz, > and my two AM bands will be at 451.2 and 751.2 respectively. Then the > hold operation simply "mask" the frequency spectrum by a sinc shape > and my 601.2Hz signal will be almost intact.You seem to have a few misconceptions here. 1. If the ADC has a 600 MHz bandwidth, then there's no need to sample/hold as long as the input is filtered to this bandwidth. 2. The sample/hold (if you had one) does the sampling. 3. The sample/hold (if you had one), when used in conjunction with data conversion, does not introduce sinc distortion. It is simply a device to hold the analog input voltage to the ADC steady while it converts the voltage to digital. 4. In any case there is no sinc distortion involved here.> Thus I won't need to do large factor decimation/filtering and save a lot of FPGA resources. > > Is this practically feasible? I asked a couple of engineers and they are not very sure..It is feasible. As you've already considered, the ADC input bandwidth is usually the main issue, but it seems you've got that covered here. You've also got to ensure your sample rate works well for the particular bandwidth you're trying to capture (I don't really have a good understanding what that is based on what you've provided here), otherwise your original spectrum might "wrap" around at Nyquist, or the positive/negative frequencies may interact in a negative way. By the way, this has been referred to as "bandpass sampling" by Rick Lyons and others - you may want to have a look at his book [lyonsthird]. --Randy @BOOK{lyonsthird, title = "{Understanding Digital Signal Processing}", edition = "third", author = "{Richard~G.~Lyons}", publisher = "Prentice Hall", year = "2011"} -- Randy Yates Digital Signal Labs http://www.digitalsignallabs.com

Reply by ●September 23, 20122012-09-23

On Sun, 23 Sep 2012 14:15:04 -0700, nick cake wrote:> Hi sampling gurus, > > I'm thinking about undersampling a 150Hz AM signal modulated to a 330MHz > carrier, thus the signal bandwidth is 300Hz. I found an ADC has 600MHz > analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the bandpass > filter is sharp enough for my my signal at 330MHz, if I use 5kHz to > sample the 330MHz, will there be any problem? > > One of my colleagues thinks there's a sinc roll-off associates with > undersampling thus one cannot use very large undersampling factor. This > is true for stealing higher harmonics out of a low Fs driven DAC, but I > don't think this is true for ADC.Your colleague is confusing the hold behavior of a DAC with the sampling behavior of an ADC. The sinc roll-off is from the hold -- which a sampling ADC does not have. (Said colleague may be further confused by the fact that sigma-delta ADCs often come with a sinc-ish filter -- don't mention it unless they start throwing data sheets around, but if they do check if it's a sigma-delta).> As I understand, the ADC can be modeled as: > 1. Sampling: multiply input continuous signal with a series of Diract > implues 2. Hold： time domain convolution with a rect window, whose width > is maximally Ts (and whose freq domain is a sinc, with first null at Fs) > 3. A-to-D: convert the held stable voltage to digital output using > proper coding > > The aliasing effect due to undersampling happens in the 1st step, thus > the 330MHz has already been "down-converted" to baseband to 601.2Hz, and > my two AM bands will be at 451.2 and 751.2 respectively. Then the hold > operation simply "mask" the frequency spectrum by a sinc shape and my > 601.2Hz signal will be almost intact. > > Thus I won't need to do large factor decimation/filtering and save a lot > of FPGA resources.It's more like the ADC can be modeled as 1: some filtering from the input bandwidth. 2: some filtering from the internal sample and hold, which -- if the IC company is honest -- is going to be rolled into the input bandwidth specification. 3: sampling itself, as you describe. 4: analog to digital conversion. But the aliasing due to undersampling _still_ happens at a wide-bandwidth point, so you're OK.> Is this practically feasible? I asked a couple of engineers and they are > not very sure..Watch for clock jitter. The clock jitter needs to be small relative to your 300MHz carrier, not relative to your 300Hz bandwidth or your 5kHz sampling rate. Make sure that the ADC doesn't get jittery at low rates, and pay careful attention to how you source the sample clock (digital logic is noisy, and that noise translates to noisy -- and hence jittery -- edges). -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com

Reply by ●September 23, 20122012-09-23

LOL I would really like this idea if they don't care about $$$ and I actually worked with 3.6GHz sampling. But the raw dropping probably won't work cause serious LP filtering would be needed before decimation, right? On Sunday, September 23, 2012 7:22:28 PM UTC-4, rickman wrote:> On 9/23/2012 5:15 PM, nick cake wrote: > > > Hi sampling gurus, > > > > > > I'm thinking about undersampling a 150Hz AM signal modulated to a 330MHz carrier, thus the signal bandwidth is 300Hz. I found an ADC has 600MHz analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the bandpass filter is sharp enough for my my signal at 330MHz, if I use 5kHz to sample the 330MHz, will there be any problem? > > > > > > One of my colleagues thinks there's a sinc roll-off associates with undersampling thus one cannot use very large undersampling factor. This is true for stealing higher harmonics out of a low Fs driven DAC, but I don't think this is true for ADC. > > > > > > As I understand, the ADC can be modeled as: > > > 1. Sampling: multiply input continuous signal with a series of Diract implues > > > 2. Hold： time domain convolution with a rect window, whose width is maximally Ts (and whose freq domain is a sinc, with first null at Fs) > > > 3. A-to-D: convert the held stable voltage to digital output using proper coding > > > > > > The aliasing effect due to undersampling happens in the 1st step, thus the 330MHz has already been "down-converted" to baseband to 601.2Hz, and my two AM bands will be at 451.2 and 751.2 respectively. Then the hold operation simply "mask" the frequency spectrum by a sinc shape and my 601.2Hz signal will be almost intact. > > > > > > Thus I won't need to do large factor decimation/filtering and save a lot of FPGA resources. > > > > > > Is this practically feasible? I asked a couple of engineers and they are not very sure.. > > > > Consider the difference between your analysis and this... > > > > Sample by flash converter at 1 GHz so that your carrier is well below > > the Nyquist rate. Then you drop 199,999 out of 200,000 samples to get a > > 5 kHz sample rate. How is this different from what you have described > > (assuming I did the ratio right :-)? > > > > Rick

Reply by ●September 23, 20122012-09-23

Hi Randy, Thanks so much for your detailed explanation! As far as I know, in the old days the sample-and-hold amp (SHA) is a separate device used to feed the ADC, and modern ADC has integrated this SHA into the converter. I don't understand why if an ADC has 600MHz bandwidth then there's no need for a sample/hold, do you mean a stand alone SHA? What I'm trying to do is break down the modern ADC behavior so as to model it mathematically to explain to my colleague what exactly is happening after a signal is fed into the ADC, one as I proposed: http://www.ti.com/lit/ds/symlink/ths0842.pdf Anyway I thank you for recommending a great book, I'll try to find one! Also thanks for reminding me the possibility of spectrum inversion or even badly folded, however for my particular Fs this will not happen (simply a Matlab simulation will tell me what exactly is being aliased down to my Nyquist band) Have a good night! On Sunday, September 23, 2012 8:46:58 PM UTC-4, Randy Yates wrote:> nick cake <> writes: > > > > > Hi sampling gurus, > > > > > > I'm thinking about undersampling a 150Hz AM signal modulated to a > > > 330MHz carrier, thus the signal bandwidth is 300Hz. I found an ADC has > > > 600MHz analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the > > > bandpass filter is sharp enough for my my signal at 330MHz, if I use > > > 5kHz to sample the 330MHz, will there be any problem? > > > > > > One of my colleagues thinks there's a sinc roll-off associates with > > > undersampling thus one cannot use very large undersampling factor. > > > This is true for stealing higher harmonics out of a low Fs driven DAC, > > > but I don't think this is true for ADC. > > > > Hey Nick, > > > > Sinc roll-off was associated with oversampling DACs in the old days > > (circa late 80s or earlier?) since those would upsample by simply > > replicating samples (instead of performing a polyphase lowpass filter). > > This creates the sinc distortion your colleague may have been thinking > > of. > > > > > As I understand, the ADC can be modeled as: > > > 1. Sampling: multiply input continuous signal with a series of Diract implues > > > 2. Hold： time domain convolution with a rect window, whose width is maximally Ts (and whose freq domain is a sinc, with first null at Fs) > > > 3. A-to-D: convert the held stable voltage to digital output using proper coding > > > > > > The aliasing effect due to undersampling happens in the 1st step, thus > > > the 330MHz has already been "down-converted" to baseband to 601.2Hz, > > > and my two AM bands will be at 451.2 and 751.2 respectively. Then the > > > hold operation simply "mask" the frequency spectrum by a sinc shape > > > and my 601.2Hz signal will be almost intact. > > > > You seem to have a few misconceptions here. > > > > 1. If the ADC has a 600 MHz bandwidth, then there's no need to > > sample/hold as long as the input is filtered to this bandwidth. > > > > 2. The sample/hold (if you had one) does the sampling. > > > > 3. The sample/hold (if you had one), when used in conjunction with > > data conversion, does not introduce sinc distortion. It is simply a > > device to hold the analog input voltage to the ADC steady while it > > converts the voltage to digital. > > > > 4. In any case there is no sinc distortion involved here. > > > > > Thus I won't need to do large factor decimation/filtering and save a lot of FPGA resources. > > > > > > Is this practically feasible? I asked a couple of engineers and they are not very sure.. > > > > It is feasible. As you've already considered, the ADC input bandwidth is > > usually the main issue, but it seems you've got that covered here. > > You've also got to ensure your sample rate works well for the particular > > bandwidth you're trying to capture (I don't really have a good > > understanding what that is based on what you've provided here), > > otherwise your original spectrum might "wrap" around at Nyquist, or the > > positive/negative frequencies may interact in a negative way. > > > > By the way, this has been referred to as "bandpass sampling" by Rick > > Lyons and others - you may want to have a look at his book [lyonsthird]. > > > > --Randy > > > > @BOOK{lyonsthird, > > title = "{Understanding Digital Signal Processing}", > > edition = "third", > > author = "{Richard~G.~Lyons}", > > publisher = "Prentice Hall", > > year = "2011"} > > > > -- > > Randy Yates > > Digital Signal Labs > > http://www.digitalsignallabs.com

Reply by ●September 23, 20122012-09-23

Hey Tim, Thanks so much for your confirmation and I am feeling much more confident now, since my colleague is a senior RF designer proposing a new architect for the next generation of one of our product. Also thanks for explaining more about the ADC behavior and jitter notice! There're a couple of more small questions: 1. As I said, the Fs I proposed is 5.1KHz, thus the 330MHz will be aliased to somewhere non-DC, thus I can do a I/Q down-conversion easily to DC, but in complex signal. If I use 5kHz, then the 330MHz will be aliased to DC, and the double side band AM will be..overlapped on the 150Hz, correct? If the phase of the AM is of great interest to us ( since it is coupled back from a high power amy to correct the phase distortion in "real-time"), will this overlap kill some of the phase measurement accuracy if we use FFT to get the phase? (actually what we need is a phase difference between two channels) 2. If we do 5kHz sampling, a 300Hz Bandpass at 330MHz would it be easy to design?? 3. In speak of jitter, if Fs is higher, such as 40MHz, the jitter effect will be less given the same frequency synthesizer chip? I'm a FPGA guy so a bit RF blind.. 4. As I replied in Randy's post, the ADC I found to be very interesting (as well as low cost) is http://www.ti.com/lit/ds/symlink/ths0842.pdf Two input channel has their own Sample/hold but share the same ADC, which is ideal for dual channel phase difference application, isn't it? Thank you guys!! It's my very first dsp group post and it rocks! On Sunday, September 23, 2012 9:39:15 PM UTC-4, Tim Wescott wrote:> On Sun, 23 Sep 2012 14:15:04 -0700, nick cake wrote: > > > > > Hi sampling gurus, > > > > > > I'm thinking about undersampling a 150Hz AM signal modulated to a 330MHz > > > carrier, thus the signal bandwidth is 300Hz. I found an ADC has 600MHz > > > analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the bandpass > > > filter is sharp enough for my my signal at 330MHz, if I use 5kHz to > > > sample the 330MHz, will there be any problem? > > > > > > One of my colleagues thinks there's a sinc roll-off associates with > > > undersampling thus one cannot use very large undersampling factor. This > > > is true for stealing higher harmonics out of a low Fs driven DAC, but I > > > don't think this is true for ADC. > > > > Your colleague is confusing the hold behavior of a DAC with the sampling > > behavior of an ADC. The sinc roll-off is from the hold -- which a > > sampling ADC does not have. > > > > (Said colleague may be further confused by the fact that sigma-delta ADCs > > often come with a sinc-ish filter -- don't mention it unless they start > > throwing data sheets around, but if they do check if it's a sigma-delta). > > > > > As I understand, the ADC can be modeled as: > > > 1. Sampling: multiply input continuous signal with a series of Diract > > > implues 2. Hold： time domain convolution with a rect window, whose width > > > is maximally Ts (and whose freq domain is a sinc, with first null at Fs) > > > 3. A-to-D: convert the held stable voltage to digital output using > > > proper coding > > > > > > The aliasing effect due to undersampling happens in the 1st step, thus > > > the 330MHz has already been "down-converted" to baseband to 601.2Hz, and > > > my two AM bands will be at 451.2 and 751.2 respectively. Then the hold > > > operation simply "mask" the frequency spectrum by a sinc shape and my > > > 601.2Hz signal will be almost intact. > > > > > > Thus I won't need to do large factor decimation/filtering and save a lot > > > of FPGA resources. > > > > It's more like the ADC can be modeled as > > > > 1: some filtering from the input bandwidth. > > > > 2: some filtering from the internal sample and hold, which -- if the IC > > company is honest -- is going to be rolled into the input bandwidth > > specification. > > > > 3: sampling itself, as you describe. > > > > 4: analog to digital conversion. > > > > But the aliasing due to undersampling _still_ happens at a wide-bandwidth > > point, so you're OK. > > > > > Is this practically feasible? I asked a couple of engineers and they are > > > not very sure.. > > > > Watch for clock jitter. The clock jitter needs to be small relative to > > your 300MHz carrier, not relative to your 300Hz bandwidth or your 5kHz > > sampling rate. Make sure that the ADC doesn't get jittery at low rates, > > and pay careful attention to how you source the sample clock (digital > > logic is noisy, and that noise translates to noisy -- and hence jittery > > -- edges). > > > > -- > > Tim Wescott > > Control system and signal processing consulting > > www.wescottdesign.com

Reply by ●September 23, 20122012-09-23

On 9/23/12 9:59 PM, nick cake wrote:> > As far as I know, in the old days the sample-and-hold amp (SHA) is a separate device used to feed the ADC, and modern ADC has integrated this SHA into the converter. I don't understand why if an ADC has 600MHz bandwidth then there's no need for a sample/hold, do you mean a stand alone SHA? >it turns out that it isn't the S/H on the ADC that causes the sinc() rolloff. it's the fact that, with a conventional DAC that the nth output sample, y[n] is the value held for y(t) for nT <= t < nT+T . it because of the hold operation on the output. it can be modeled as being driven by a string impulses and resulting in a string of piecewise constant pulse. the linear system that does this is called a "zero-order hold" and there isn't really such a thing, physically. it's a conceptual model to understand the difference from the theoretical ideal (a string of impulses going into a perfect brickwall low-pass filter) to the practical reality (a piecewise constant function) in the output of the DAC.> What I'm trying to do is break down the modern ADC behavior so as to model it mathematically to explain to my colleague what exactly is happening after a signal is fed into the ADC, one as I proposed: > > http://www.ti.com/lit/ds/symlink/ths0842.pdfit's not the 25 ns hold time for those S/H in the chip. it's whatever the sampling window is to charge up the hold capacitor. i think it's the "Aperture delay time", t_d(a) = 3 ns, which determines how the sinc rolloff is for the input analog signal. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge."

Reply by ●September 24, 20122012-09-24

"nick cake" <nickcake@gmail.com> wrote in message news:706ecb0c-56d7-421e-8b5a-efa425e794f8@googlegroups.com... Hi sampling gurus, I'm thinking about undersampling a 150Hz AM signal modulated to a 330MHz carrier, thus the signal bandwidth is 300Hz. I found an ADC has 600MHz analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the bandpass filter is sharp enough for my my signal at 330MHz, if I use 5kHz to sample the 330MHz, will there be any problem? One of my colleagues thinks there's a sinc roll-off associates with undersampling thus one cannot use very large undersampling factor. This is true for stealing higher harmonics out of a low Fs driven DAC, but I don't think this is true for ADC. As I understand, the ADC can be modeled as: 1. Sampling: multiply input continuous signal with a series of Diract implues 2. Hold? time domain convolution with a rect window, whose width is maximally Ts (and whose freq domain is a sinc, with first null at Fs) 3. A-to-D: convert the held stable voltage to digital output using proper coding The aliasing effect due to undersampling happens in the 1st step, thus the 330MHz has already been "down-converted" to baseband to 601.2Hz, and my two AM bands will be at 451.2 and 751.2 respectively. Then the hold operation simply "mask" the frequency spectrum by a sinc shape and my 601.2Hz signal will be almost intact. Thus I won't need to do large factor decimation/filtering and save a lot of FPGA resources. Is this practically feasible? I asked a couple of engineers and they are not very sure..

Reply by ●September 24, 20122012-09-24

On Sunday, September 23, 2012 2:15:04 PM UTC-7, nick cake wrote:> Hi sampling gurus, > > I'm thinking about undersampling a 150Hz AM signal modulated to a 330MHz carrier, thus the signal bandwidth is 300Hz. I found an ADC has 600MHz analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the bandpass filter is sharp enough for my my signal at 330MHz, if I use 5kHz to sample the 330MHz, will there be any problem? > > ...> Is this practically feasible? I asked a couple of engineers and they are not very sure..It is common for beginners to posting in comp.dsp to ask interesting theoretical questions followed by the killer question: "Is it feasible." It is traditional for the OP to be asked what the whole system is and the purpose of the system, because this has a tremendous influence on feasibility. (Don't worry, it is also traditional for more experienced posters to leave out the necessary description of the whole system.) On Sunday, September 23, 2012 7:12:22 PM UTC-7, nick cake wrote:> Hey Tim, > ...> 1. As I said, the Fs I proposed is 5.1KHz, thus the 330MHz will be aliased to somewhere non-DC, thus I can do a I/Q down-conversion easily to DC, but in complex signal. If I use 5kHz, then the 330MHz will be aliased to DC, and the double side band AM will be..overlapped on the 150Hz, correct? If the phase of the AM is of great interest to us ( since it is coupled back from a high power amy to correct the phase distortion in "real-time"), will this overlap kill some of the phase measurement accuracy if we use FFT to get the phase? (actually what we need is a phase difference between two channels) > > 2. If we do 5kHz sampling, a 300Hz Bandpass at 330MHz would it be easy to design?? > ...I think that the design of a 300Hz bandwidth filter at 330Mhz will be interesting. From your mention of "phase difference", you will apparently need two. Will the application require phase matching? Will the application require amplitude matching? These are examples of why the nature of the rest of the system matters. Looking at another type of jitter effects, how accurately is the 330MHz carrier generated? For example, a specification of an accuracy 1 part per million at 330MHz would put your sidebands typically outside of the bandpass 300 Hz centered at a nominal 330MHz. That's one real world issue. Another is: Are your two channels from (exactly) to same source or do they have independent frequency errors? Then, what accuracy (amplitude and delay) do you need in the passband? What rejection do you need in the stopband to reject the 600Mhz/5.1KHz (or about 120000) noise bands aliased into your samples from the A/D input bandwidth? What kind of interference do you need to reject? Even specifying the anti-alias filter is an exercise. Do you need to widen the passband to account for the range of possible frequencies you need to capture? Does that influence the sampling frequency required? Lots of questions depend on the details you have not yet provided. Good luck! Dale B. Dalrymple