>> It is common for beginners to posting in comp.dsp to ask interestingtheoretical questions followed by the killer question: "Is it feasible." Yes... We all may learn a little from the question and its implications. But one thing is near-certain: It won't lead to a working design: Common sense tells me that someone who had the expertise to really make "extreme undersampling" work in hardware wouldn't need to ask a conceptual question. It seems like a good textbook exercise, actually, as it's a pretty idea leading to such a rotten design. For a concept demo, yes, I can make it work, more or less. All I need is a 15 k€ sampling scope, call it "ADC", and a 30 k€ signal generator as sampling clock, triggering the scope. And five lines of code to take periodic readings.
Is it possible to use very large undersampling factor (using 5.1kHz to sample 330MHz)?
Started by ●September 23, 2012
Reply by ●September 24, 20122012-09-24
Reply by ●September 24, 20122012-09-24
Reply by ●September 24, 20122012-09-24
On 24.9.12 12:15 , nick cake wrote:> Hi sampling gurus, > > I'm thinking about undersampling a 150Hz AM signal modulated to a 330MHz carrier, thus the signal bandwidth is 300Hz. I found an ADC has 600MHz analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the bandpass filter is sharp enough for my my signal at 330MHz, if I use 5kHz to sample the 330MHz, will there be any problem? > > One of my colleagues thinks there's a sinc roll-off associates with undersampling thus one cannot use very large undersampling factor. This is true for stealing higher harmonics out of a low Fs driven DAC, but I don't think this is true for ADC. > > As I understand, the ADC can be modeled as: > 1. Sampling: multiply input continuous signal with a series of Diract implues > 2. Hold： time domain convolution with a rect window, whose width is maximally Ts (and whose freq domain is a sinc, with first null at Fs) > 3. A-to-D: convert the held stable voltage to digital output using proper coding > > The aliasing effect due to undersampling happens in the 1st step, thus the 330MHz has already been "down-converted" to baseband to 601.2Hz, and my two AM bands will be at 451.2 and 751.2 respectively. Then the hold operation simply "mask" the frequency spectrum by a sinc shape and my 601.2Hz signal will be almost intact. > > Thus I won't need to do large factor decimation/filtering and save a lot of FPGA resources. > > Is this practically feasible? I asked a couple of engineers and they are not very sure.. >Attempting to listen to ILS glide path? -- Tauno Voipio
Reply by ●September 24, 20122012-09-24
I'm not suggesting that you do it this way, I am talking about analysis. You said there is a band pass filter before the ADC, so why would you need a filter before the decimation? BTW, if you add a digital filter, it won't be a low pass. It would be a band pass since the signal is not at the low frequency until after you do the decimation and then it is too late. So do you need additional filtering or is your analog band pass adequate? I repeat my question. In terms of the resulting signal, how is the process I described different from what you have described? This should help you understand what is going on in your case and what is needed to make it work. Rick On 9/23/2012 9:51 PM, nick cake wrote:> LOL I would really like this idea if they don't care about $$$ and I actually worked with 3.6GHz sampling. But the raw dropping probably won't work cause serious LP filtering would be needed before decimation, right? > > On Sunday, September 23, 2012 7:22:28 PM UTC-4, rickman wrote: >> On 9/23/2012 5:15 PM, nick cake wrote: >> >>> Hi sampling gurus, >> >>> >> >>> I'm thinking about undersampling a 150Hz AM signal modulated to a 330MHz carrier, thus the signal bandwidth is 300Hz. I found an ADC has 600MHz analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the bandpass filter is sharp enough for my my signal at 330MHz, if I use 5kHz to sample the 330MHz, will there be any problem? >> >>> >> >>> One of my colleagues thinks there's a sinc roll-off associates with undersampling thus one cannot use very large undersampling factor. This is true for stealing higher harmonics out of a low Fs driven DAC, but I don't think this is true for ADC. >> >>> >> >>> As I understand, the ADC can be modeled as: >> >>> 1. Sampling: multiply input continuous signal with a series of Diract implues >> >>> 2. Hold： time domain convolution with a rect window, whose width is maximally Ts (and whose freq domain is a sinc, with first null at Fs) >> >>> 3. A-to-D: convert the held stable voltage to digital output using proper coding >> >>> >> >>> The aliasing effect due to undersampling happens in the 1st step, thus the 330MHz has already been "down-converted" to baseband to 601.2Hz, and my two AM bands will be at 451.2 and 751.2 respectively. Then the hold operation simply "mask" the frequency spectrum by a sinc shape and my 601.2Hz signal will be almost intact. >> >>> >> >>> Thus I won't need to do large factor decimation/filtering and save a lot of FPGA resources. >> >>> >> >>> Is this practically feasible? I asked a couple of engineers and they are not very sure.. >> >> >> >> Consider the difference between your analysis and this... >> >> >> >> Sample by flash converter at 1 GHz so that your carrier is well below >> >> the Nyquist rate. Then you drop 199,999 out of 200,000 samples to get a >> >> 5 kHz sample rate. How is this different from what you have described >> >> (assuming I did the ratio right :-)? >> >> >> >> Rick >
Reply by ●September 24, 20122012-09-24
You are trying to reduce digital complexity by adding analog complexity (ei the very sharp analog pre-filter). In general this is the opposite of what modern approaches are all about. I don't know if you have much experience with digital filters, but if you naively entered a brick wall filter requirement into Matlab and found you needed a lots of taps, and this drove you to try the under-sampling approach, then I would urge you to read up on multi-rate decimation filters with the early stages of the filter done using a CIC filter and the noble identities (google Hogenauer). I can pretty much guarantee that this will dramatically reduce your fpga requirements and allow you to operate the converter at a higher rate. Some amount of under-sampling may be appropriate, but going to such an extreme is not a good idea. Bob
Reply by ●September 24, 20122012-09-24
nick cake <nickcake@gmail.com> wrote:> I'm thinking about undersampling a 150Hz AM signal modulated to a > 330MHz carrier, thus the signal bandwidth is 300Hz. > I found an ADC has 600MHz analogue bandwidth, and minimum Fs to > be 5.1kHz. Suppose the bandpass filter is sharp enough for my > my signal at 330MHz, if I use 5kHz to sample the 330MHz, > will there be any problem?Never having actually designed one, wouldn't it be usual to mix down to a lower frequency for filtering and sampling? If needed, I think the LO could be phase locked to some reference such that phase information was retained. -- glen
Reply by ●September 24, 20122012-09-24
On 9/23/2012 10:12 PM, nick cake wrote:> Hey Tim, > > Thanks so much for your confirmation and I am feeling much more confident now, since my colleague is a senior RF designer proposing a new architect for the next generation of one of our product. > > Also thanks for explaining more about the ADC behavior and jitter notice! > > There're a couple of more small questions: > > 1. As I said, the Fs I proposed is 5.1KHz, thus the 330MHz will be aliased to somewhere non-DC, thus I can do a I/Q down-conversion easily to DC, but in complex signal. If I use 5kHz, then the 330MHz will be aliased to DC, and the double side band AM will be..overlapped on the 150Hz, correct? If the phase of the AM is of great interest to us ( since it is coupled back from a high power amy to correct the phase distortion in "real-time"), will this overlap kill some of the phase measurement accuracy if we use FFT to get the phase? (actually what we need is a phase difference between two channels) > > 2. If we do 5kHz sampling, a 300Hz Bandpass at 330MHz would it be easy to design??Time out! Are you talking about a digital filter after you have sampled at 5.1 kHz? If so it is too late to filter out signals outside of the 2.55 kHz bandwidth of the resulting digital signal. If you are talking about an analog filter, I think it will be exceedingly hard to design such a filter, no? Maybe there are some advanced techniques in SAW filters or something that can do this, but I am not aware of them.> 3. In speak of jitter, if Fs is higher, such as 40MHz, the jitter effect will be less given the same frequency synthesizer chip?Jitter is jitter. For a larger frequency the period is smaller, so a given amount of jitter in picoseconds is proportionally larger. The point is that even though you are down-converting to a 5.1 kHz sample rate, the original signal is centered at 330 MHz and this is what you need to sample with stability. At 330 MHz the clock period is about 3 ns, so 1 ns is a third of a cycle! Even 100 ps is about 12 degrees. You are going to need a VERY stable 5.1 kHz clock.> I'm a FPGA guy so a bit RF blind..This is stuff you need to learn if you are going to work in receivers. In a receiver the FPGA stuff is make or break for performance!> 4. As I replied in Randy's post, the ADC I found to be very interesting (as well as low cost) is http://www.ti.com/lit/ds/symlink/ths0842.pdf > > Two input channel has their own Sample/hold but share the same ADC, which is ideal for dual channel phase difference application, isn't it? > > Thank you guys!! It's my very first dsp group post and it rocks!
Reply by ●September 24, 20122012-09-24
On Sun, 23 Sep 2012 14:15:04 -0700 (PDT), nick cake <nickcake@gmail.com> wrote:>Hi sampling gurus, > >I'm thinking about undersampling a 150Hz AM signal modulated to a 330MHz ca= >rrier, thus the signal bandwidth is 300Hz. I found an ADC has 600MHz analog= >ue bandwidth, and minimum Fs to be 5.1kHz. Suppose the bandpass filter is s= >harp enough for my my signal at 330MHz, if I use 5kHz to sample the 330MHz,= > will there be any problem? > >One of my colleagues thinks there's a sinc roll-off associates with undersa= >mpling thus one cannot use very large undersampling factor. This is true fo= >r stealing higher harmonics out of a low Fs driven DAC, but I don't think t= >his is true for ADC. > >As I understand, the ADC can be modeled as: >1. Sampling: multiply input continuous signal with a series of Diract implu= >es >2. Hold=EF=BC=9A time domain convolution with a rect window, whose width is= > maximally Ts (and whose freq domain is a sinc, with first null at Fs) >3. A-to-D: convert the held stable voltage to digital output using proper c= >oding=20 > >The aliasing effect due to undersampling happens in the 1st step, thus the = >330MHz has already been "down-converted" to baseband to 601.2Hz, and my two= > AM bands will be at 451.2 and 751.2 respectively. Then the hold operation = >simply "mask" the frequency spectrum by a sinc shape and my 601.2Hz signal = >will be almost intact. > >Thus I won't need to do large factor decimation/filtering and save a lot of= > FPGA resources. > >Is this practically feasible? I asked a couple of engineers and they are no= >t very sure..It's theoretically possible: http://www.dsprelated.com/showarticle/175.php but, as others have mentioned, there are some practical barriers. Creating a bandpass filter with <2500Hz BW at 330 MHz will require an extremely high Q-factor, which is very difficult to achieve. Also, as the center frequency increases the aperture jitter of the sampling system becomes important in order to maintain SNR in the sampled signal. Eric Jacobsen Anchor Hill Communications www.anchorhill.com
Reply by ●September 24, 20122012-09-24
Hi Dale, Thanks for your great insights by pop out quite a few points to be clarified! I post this question initially just to confirm that there's no such sinc attenuation when it comes to undersampling as it was used in DAC tricks. Then it turns out this is theoretically correct and I became greedy to know more about implementation.. Hey Tauno you are deadly right, it's about ILS and compensation the phase difference between two generated channels. Get back to Dale, yes I guess as many pointed out, a 300Hz at 330MHz BPF will be a pain in the ass. My point is actually that instead of using 40MHz sampling, we can use something less, so that to save FPGA resources/power/processing time.. The 5.1kHz is mentioned as a sort of extreme example. We surely need to consider the analogy BPF design easiness to determine the proper Fs. I strongly agree that without properly stated the spec of the system, it's a bit hard to give meaningful answers. But in fact I'm not sure what exactly the spec is..as I'm not fully involved in the design process. Just being asked for DSP supports from time to time. So I'll do my best. I believe the two channels are from the same source and wrpt to phase matching or amplitude matching, I'm not sure what do you mean by that.. again what we want to do is to couple back a bit of the high power amp output then detect phase difference between amps in two channels, and compensate it in the generation signals. Also the AM modulation index (carrier/side band amp ratio) is of interest, thus I proposed an FFT to do them at the same shot. What kind of reject to those noise that will be fold back to baseband I can't really tell.. Generally two things I believe is a good news for me: 1. by using a sampling frequency greatly higher than needed(minimum Fs should be 600Hz as my AM baseband signal is 150Hz), thus by proper digital filtering and decimation, there's quite a few processing gain there, right? 2.Using the same jitter/phase noise grade clock source, generating a lower frequency signal will have less jitter than a higher frequency signal, thus using something lower than 40MHz will have less jitter in the sampling clock if using the same clock source but generating 40MHz, right?(e.g. simply divide the 40MHz by 2 will reduce the jitter, right?) I think the steps to go is: 1. determine how much effort/$ we want to invest in the analog BPF 2. the minimum Fs is thus determined Correct me if I'm not getting at the point! On Monday, September 24, 2012 1:01:29 AM UTC-4, dbd wrote:> On Sunday, September 23, 2012 2:15:04 PM UTC-7, nick cake wrote: > > > Hi sampling gurus, > > > > > > I'm thinking about undersampling a 150Hz AM signal modulated to a 330MHz carrier, thus the signal bandwidth is 300Hz. I found an ADC has 600MHz analogue bandwidth, and minimum Fs to be 5.1kHz. Suppose the bandpass filter is sharp enough for my my signal at 330MHz, if I use 5kHz to sample the 330MHz, will there be any problem? > > > > > > ... > > > > > Is this practically feasible? I asked a couple of engineers and they are not very sure.. > > > > It is common for beginners to posting in comp.dsp to ask interesting theoretical questions followed by the killer question: "Is it feasible." It is traditional for the OP to be asked what the whole system is and the purpose of the system, because this has a tremendous influence on feasibility. (Don't worry, it is also traditional for more experienced posters to leave out the necessary description of the whole system.) > > > > On Sunday, September 23, 2012 7:12:22 PM UTC-7, nick cake wrote: > > > Hey Tim, > > > ... > > > > > 1. As I said, the Fs I proposed is 5.1KHz, thus the 330MHz will be aliased to somewhere non-DC, thus I can do a I/Q down-conversion easily to DC, but in complex signal. If I use 5kHz, then the 330MHz will be aliased to DC, and the double side band AM will be..overlapped on the 150Hz, correct? If the phase of the AM is of great interest to us ( since it is coupled back from a high power amy to correct the phase distortion in "real-time"), will this overlap kill some of the phase measurement accuracy if we use FFT to get the phase? (actually what we need is a phase difference between two channels) > > > > > > 2. If we do 5kHz sampling, a 300Hz Bandpass at 330MHz would it be easy to design?? > > > ... > > > > I think that the design of a 300Hz bandwidth filter at 330Mhz will be interesting. From your mention of "phase difference", you will apparently need two. Will the application require phase matching? Will the application require amplitude matching? These are examples of why the nature of the rest of the system matters. > > > > Looking at another type of jitter effects, how accurately is the 330MHz carrier generated? For example, a specification of an accuracy 1 part per million at 330MHz would put your sidebands typically outside of the bandpass 300 Hz centered at a nominal 330MHz. That's one real world issue. Another is: Are your two channels from (exactly) to same source or do they have independent frequency errors? > > > > Then, what accuracy (amplitude and delay) do you need in the passband? What rejection do you need in the stopband to reject the 600Mhz/5.1KHz (or about 120000) noise bands aliased into your samples from the A/D input bandwidth? What kind of interference do you need to reject? Even specifying the anti-alias filter is an exercise. > > > > Do you need to widen the passband to account for the range of possible frequencies you need to capture? Does that influence the sampling frequency required? Lots of questions depend on the details you have not yet provided. > > > > Good luck! > > > > Dale B. Dalrymple
Reply by ●September 24, 20122012-09-24
Hi mnentwig, Yes my initial idea is to prove that theoretically, it's correct, as many has this wrong impression it will have sinc problem. I'm not saying we will do a design in this way so please don't say rotten design. Also I'm not getting what do you mean a demo by a driving a sampling scope by a "good?" sig gen.. anyway, your euro sign displays well in Chrome~ On Monday, September 24, 2012 1:38:56 AM UTC-4, mnentwig wrote:> >> It is common for beginners to posting in comp.dsp to ask interesting > > theoretical questions followed by the killer question: "Is it feasible." > > > > Yes... We all may learn a little from the question and its implications. > > But one thing is near-certain: It won't lead to a working design: > > Common sense tells me that someone who had the expertise to really make > > "extreme undersampling" work in hardware wouldn't need to ask a conceptual > > question. It seems like a good textbook exercise, actually, as it's a > > pretty idea leading to such a rotten design. > > > > For a concept demo, yes, I can make it work, more or less. All I need is a > > 15 k� sampling scope, call it "ADC", and a 30 k� signal generator as > > sampling clock, triggering the scope. And five lines of code to take > > periodic readings.
