Custom decimation filter from PCM4222 multibit modulator output using an FPGA

Hi !
I'm new to DSP and trying to make smth out of it for a couple of days.
I'm familiar with Altera FPGA's -> so far i was rather doing bits manipulation, translating one audio proctol (i2s,left-justified, aes/ebu etc.) to another - with the control of external uC. 

Now i have to design a decimation filter for sigma-delta ADC PCM4222:
http://www.ti.com/lit/ds/symlink/pcm4222.pdf

It has lots of options -> DSD output (SACD), 24 bit 216kHz PCM output (I2S) and a 6-bit sigma-delta modulator output with 6.144 MHz clock. So one can make his own decimation filter. Info about the modulator starts at page 26 of PCM4222 datasheet.

And i have to design a decimation filter that would give me from this 384 kHz 24 bit PCM. I have chosen this ADC because i need both DSD and PCM as high as 384kHz.

So my questions are:
1) 6 bit means that it is 6bit quantization value - so it gives 64 levels every clock cycle for an oversampled audio signal? I read on TI forums that it won't go FULL SCALE - so it means that i would get those levels?
2) Decimation is basically taking every M'th sample so if i wanted to make from my modulator output 384 kHz 6-bit PCM value would i have to take to the output one of  6.144Mhz/0.384Mhz = 16 samples and also add low pass filter with cut off frequency of 384/2 = 192 kHz ?
3) How do i get wider bit lenght for example my 24 bit 384 kHz. Should i integrate (sum) couple of those 6 bit samples and then take onlu M'th sample ?
4) Is it smth like when i have 6 bit at 6.144 Mhz, then i can get 12 bits at 3.072 Mhz, 24 bits at 1.536 Mhz. And after those steps i take every M'th sample to the output ( M=1.536/0.384= 4).  And after then i should make an low pass filter at cut off freq. of 192 kHz?
5) When i will have my 24 bit data at 384kHz, 384 would be my word clock, to serialize this 24 bit data and send it to the other device or DAC with I2S protcol, i would have to have also a bit clock (64 times world clock => 0.384Mhz * 64 = 24.576 Mhz. 64 times for left and right channel). Should i use 6.144 Mhz modulator output clock to generate this 24.576 Mhz clock?
6) So far i was talking about only one channel. Modulator output according to page 27 of PCM4222 has WCKO = which for 48kHz fs equals to 6.144 Mhz and MCKI which is 2 times faster 12.288 Mhz. It's used to distinct left and right channel.
Is it neccessary to create two exactly the same filters in hardware or can i somehow run my filter two times faster, and in one half of the cycle to filter out left channel and then in the second cycle filter out the right channel (basically using the same hardware).
7) What implementation would be the best for an FPGA and for good audible results. I was planning to use 6k LE cyclone IV device with 15 18x18bit multpliers. I suppose that group delay from the Filter is a great concern here ? the lower the better? I have read about CIC filters with compesation, not so many hardware needed for implementation, but also a big group delay. How about using half band filters? As farest i have seen they had both low resources needed and average high group delay.

I would be very appreciated if You could clear some things up for me :)
thanks for any help and best regards
saint0r

On Mon, 22 Oct 2012 13:32:44 -0700, saint0r wrote:

> Hi !
> I'm new to DSP and trying to make smth out of it for a couple of days.
> I'm familiar with Altera FPGA's -> so far i was rather doing bits
> manipulation, translating one audio proctol (i2s,left-justified, aes/ebu
> etc.) to another - with the control of external uC.
> 
> Now i have to design a decimation filter for sigma-delta ADC PCM4222:
> http://www.ti.com/lit/ds/symlink/pcm4222.pdf
> 
> It has lots of options -> DSD output (SACD), 24 bit 216kHz PCM output
> (I2S) and a 6-bit sigma-delta modulator output with 6.144 MHz clock. So
> one can make his own decimation filter. Info about the modulator starts
> at page 26 of PCM4222 datasheet.
> 
> And i have to design a decimation filter that would give me from this
> 384 kHz 24 bit PCM. I have chosen this ADC because i need both DSD and
> PCM as high as 384kHz.
> 
> So my questions are:
> 1) 6 bit means that it is 6bit quantization value - so it gives 64
> levels every clock cycle for an oversampled audio signal? I read on TI
> forums that it won't go FULL SCALE - so it means that i would get those
> levels?

Not being familiar with the part, I'm not sure about the not going full 
scale bit.  It probably means that it doesn't go down to -32, or up to 
+31 (or 0 to 63).  Or, worse, that it does not do so gracefully.

So, it gives something less than 64 levels each clock cycle, and if it's 
a decent sigma-delta modulator, then it does so in a way that's 
guaranteed to push the quantization noise into higher frequencies.

> 2) Decimation is basically taking every M'th sample so if i
> wanted to make from my modulator output 384 kHz 6-bit PCM value would i
> have to take to the output one of  6.144Mhz/0.384Mhz = 16 samples and
> also add low pass filter with cut off frequency of 384/2 = 192 kHz ?

You would precede the decimator by the low-pass filter.  Nyquist didn't 
say that if you want to sample at X that you should use a cutoff-filter 
at X/2, though:

http://www.wescottdesign.com/articles/Sampling/sampling.pdf

> 3) > How do i get wider bit lenght for example my 24 bit 384 kHz.
> Should i integrate (sum) couple of those 6 bit samples and then take
> onlu M'th sample ?

Your low-pass filter shouldn't be nearly so simple.  You should run the 
6144kHz signal through a lowpass filter operating at that frequency, and 
running sufficient data path widths so that you have 24 good bits coming 
out (assuming that there's actually that much data there).  Then _after_ 
you have 24 bits worth of data you should decimate.

Depending on the filter needed, you can probably run the filter at your 
output rate, but you'll still need to take in all the input samples, and 
you'll probably need more than 16 of them per output sample if you want 
better than 10 bits of precision.

> 4) Is it smth like when i have 6 bit at 6.144 Mhz,
> then i can get 12 bits at 3.072 Mhz, 24 bits at 1.536 Mhz. And after 
> those steps i take every M'th sample to the output 
> ( M=1.536/0.384= 4).  And after then i should make an low pass filter
> at cut off freq. of 192 kHz?

It's more complicated than that.  The data sheet does not seem to show 
the quantization noise vs. frequency, which is really odd in a sigma-
delta converter that's designed so you can add your own decimation filter.

If the quantization noise were rising at 6dB/decade, then for each 
halving of the output rate, you'd add one bit.  12dB/decade, then two 
bits/halving, etc.

But TI doesn't say.  And, at any rate, they give a best-case SNR of 
108dB, which means that the effective number of bits is just 18; the rest 
of the bits are (depending on your attitude) either "marketing bits" or 
they're there to make sure that output quantization is not an issue.

You should pick up more than four bits, but again, I'm not sure just how 
many.  To get the nice steep cutoff that they show for their lowpass 
filter you'll have a low-pass filter that's longer than 16 taps, and more 
complex than the evenly-weighted taps you'd see in a CIC filter.

> 5) When i will have my 24 bit data at 384kHz, 384 would be my word
> clock,
> to serialize this 24 bit data and send it to the other device or DAC
> with I2S protcol, i would have to have also a bit clock (64 times world
> clock => 0.384Mhz * 64 = 24.576 Mhz. 64 times for left and right
> channel). Should i use 6.144 Mhz modulator output clock to generate this
> 24.576 Mhz clock? 

That's a system-level question that has much more to do with your circuit 
than with DSP in general.  If you clock everything in the system off of 
that 6.144MHz master clock it'll certainly simplify things in other ways.

> 6) So far i was talking about only one channel.
> Modulator output according to page 27 of PCM4222 has WCKO = which for
> 48kHz fs equals to 6.144 Mhz and MCKI which is 2 times faster 12.288
> Mhz. It's used to distinct left and right channel. Is it neccessary to
> create two exactly the same filters in hardware or can i somehow run my
> filter two times faster, and in one half of the cycle to filter out left
> channel and then in the second cycle filter out the right channel
> (basically using the same hardware). 

You can go either way; that's a tactical decision that depends on how 
fast you want to clock your FPGA vs. how big you want it to be.

> 7) What implementation would be the
> best for an FPGA and for good audible results. I was planning to use 6k
> LE cyclone IV device with 15 18x18bit multpliers. I suppose that group
> delay from the Filter is a great concern here ? the lower the better? I
> have read about CIC filters with compesation, not so many hardware
> needed for implementation, but also a big group delay. How about using
> half band filters? As farest i have seen they had both low resources
> needed and average high group delay.

Now that's getting outside of my main expertise: I have ears made of lead 
(it saves on radios) so I'm not much of an Audio Guy.

I doubt that straight delay is an issue: I suspect that you're more 
concerned with varying group delay.  There's no reason you couldn't make 
a compensated CIC with a constant group delay.

BUT:  I've read here that the inevitable pre-echo from such filters isn't 
a good thing in audio applications: it's better to use a minimum-phase 
filter even if that means accepting the inevitable variation in group 
delay with frequency.  You can have one or the other; you need to listen 
to each one to decide which works better for you.

> I would be very appreciated if You could clear some things up for me :)
> thanks for any help and best regards
> saint0r





-- 
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

Tim Wescott <tim@seemywebsite.com> wrote:
> On Mon, 22 Oct 2012 13:32:44 -0700, saint0r wrote:

(snip) 
>> Now i have to design a decimation filter for sigma-delta ADC PCM4222:
>> http://www.ti.com/lit/ds/symlink/pcm4222.pdf
 

(big snip, mostly on the analog side, but some on the digital side,
too.)

>> 6) So far i was talking about only one channel.
>> Modulator output according to page 27 of PCM4222 has WCKO = which for
>> 48kHz fs equals to 6.144 Mhz and MCKI which is 2 times faster 12.288
>> Mhz. It's used to distinct left and right channel. Is it neccessary to
>> create two exactly the same filters in hardware or can i somehow run my
>> filter two times faster, and in one half of the cycle to filter out left
>> channel and then in the second cycle filter out the right channel
>> (basically using the same hardware). 

> You can go either way; that's a tactical decision that depends on how 
> fast you want to clock your FPGA vs. how big you want it to be.

There are many more choices than that. 

For the fastest rate, you start with separate fully pipelined
filters, my usual favorite is systolic arrays.

If you don't need that fast, then you can reuse some of the
hardware, starting with sharing the hardware between channels,
but also reusing hardware like multipliers.

Depending on how much pipelining you do, usual FPGAs are in the
100MHz range. A little faster if you pipeline every stage,
a little slower if you do less pipelining.

At 6.144MHz, you might be able to reuse the multplier 16 times
for each input sample. 

http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

Says about 5ns for the multiplier. By the time you add the rest
of the logic around it, 100MHz might be about right.

-- glen

Hi, 
thanks for your replies !
Yea it's going to be fun to design the filter :) lots of ways to do it, lot's of trade-offs to consider :)

> 
> Your low-pass filter shouldn't be nearly so simple.  You should run the 
> 
> 6144kHz signal through a lowpass filter operating at that frequency, and 
> 
> running sufficient data path widths so that you have 24 good bits coming 
> 
> out (assuming that there's actually that much data there).  Then _after_ 
> 
> you have 24 bits worth of data you should decimate.
> 

I still don't get the wider bit lenght ? Should i before decimation(low pass filtering + downsampling) sum couple of samples of my 6 bit signal ? Is it as simple as adding a samples toghether, when you sum two 6 bit samples your result could be 7 bits long at max. Does it means i would have to sum at least 24-6 = 18 samples? And after i sum those 18 samples i low pass filter the sums, and then downsample ?

------
Glen do you have some good materials, or do you know a good book about  systolic arrays ?

best regards
saint0r

On Mon, 22 Oct 2012 22:26:33 -0700, saint0r wrote:

> Hi,
> thanks for your replies !
> Yea it's going to be fun to design the filter :) lots of ways to do it,
> lot's of trade-offs to consider :)
> 
> 
>> Your low-pass filter shouldn't be nearly so simple.  You should run the
>> 
>> 6144kHz signal through a lowpass filter operating at that frequency,
>> and
>> 
>> running sufficient data path widths so that you have 24 good bits
>> coming
>> 
>> out (assuming that there's actually that much data there).  Then
>> _after_
>> 
>> you have 24 bits worth of data you should decimate.
>> 
>> 
> I still don't get the wider bit lenght ?

Then you don't understand sigma-delta converters, and all that you're 
doing now is fumbling in the dark.  In a big room, with pitfalls.

Here's the short-short course:

A sigma-delta converter is _not_ just a 6-bit (or one-bit) converter.

When you convert to some finite number of bits, you are left with some 
error, because you're putting a continuous value into your converter, and 
you're selecting one of N possible output values (2 in the case of a 1-
bit converter, 64 in your case).  This error is called quantization 
error, or quantization noise.

With an ordinary ADC, the output of the ADC only depends on the input 
(and maybe some noise); this means that the quantization error stays 
constant, which, in turn, means that it is what it is, and you're stuck 
with it.

A sigma-delta converter puts the ADC inside of a feedback loop, and the 
feedback loop is made to insure that the average error coming out of the 
built-in ADC is zero.  The effect of this ADC-and-feedback combination is 
that the ADC output dithers: each ADC output has quantization error (in 
fact, on average the error itself is greater), but the _average_ 
quantization error is zero.

You'll see this process called "noise shaping", because the overall 
effect is to take some fixed (for each particular input voltage) amount 
of error, and turn it into error that is greater overall, but whose 
spectrum goes to zero at DC, and to some maximum at Nyquist.

What the particular spectrum of this noise is depends on the converter 
and on the input voltage (sigma-delta converter noise is code-dependent; 
making it code-dependent and unobjectionable is the subject of quite a 
bit of effort on the manufacturer's part).

> Should i before decimation(low
> pass filtering + downsampling) sum couple of samples of my 6 bit signal
> ? Is it as simple as adding a samples toghether, when you sum two 6 bit
> samples your result could be 7 bits long at max. Does it means i would
> have to sum at least 24-6 = 18 samples? And after i sum those 18 samples
> i low pass filter the sums, and then downsample ?

Now that you know that there is information in the dithering of the ADC 
output, I hope that you know the answer to your question.  I've already 
given my suggestion, I suggest that you go back and re-read it.

I would also suggest that if you're looking for books, you get yourself a 
book on sigma-delta converters.  The whole thing will be explained, then, 
including (one hopes) information on the making of decimation filters.

Here's an article on making cheezy little 1st-order sigma-delta 
converters to extend DAC resolution in control loops.  Reading it and 
thinking you're all educated would be like showing up at a motorcycle 
drag race with a scooter, but it should at least familiarize you with the 
terms:

http://www.embedded.com/design/configurable-systems/4006431/Sigma-delta-
techniques-extend-DAC-resolution

Or, for the URL-length-challenged: http://tinyurl.com/9dr5y5p

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com