I am looking to use a delta sigma (DS) converter with a minimal
footprint in an FPGA, both in terms of LUT usage and power consumption.
Lattice Semiconductor has an app note on a design, but it is not much
like what I find described elsewhere. I'm not clear on how to analyze
this approach or how well it will work in my application.
The main feature is that it uses the LVDS input as a comparator which I
believe equates to the quantizer in the various DS descriptions I have
read. I believe this comparator also combines the quantizer with a
summation of the input and the shaped error feedback. These papers also
include a dither input which is summed to the signal between the summed
input and the quantizer. Obviously if the input summation and the
quantizer are combined the dither can't be injected here.
In fact, the error term is calculated by subtracting the summed input
from the quantized output. So this also can't be done. But then I'm
not sure exactly what this error term would be with a one bit
quantizer... I guess the input to the quantizer is intended to be
digital, but more than 1 bit.
I'm having trouble picturing the DS conversions I see described in the
context of a circuit I can realize in the FPGA using the LVDS input as
the comparator. Am I not analyzing this correctly?
The circuit Lattice describes is this...
|\
input -->|+\ +----+ +------+ +--------+
| >----|D Q|---+---|En Cnt|-----| Filter |---> Output
+--->|-/ | | | | | | |
| |/ |Clk | | |Clk | |Clk |
| +----+ | +------+ +--------+
| |
+--------+--\/\/\-----+
| R
= C
|
V
The counter is allowed to run for some number of input samples and then
reset to give a decimation by N. This value is run through the IIR
filter and further decimated by M to produce the output samples.
I'm sure this is far from an optimal design. But I can't really figure
out how to improve it given the limitations of using the LVDS input as a
comparator.
Any suggestions? Any thoughts on how to analyze this?
I'm tempted to try to design an async circuit as a voltage to frequency
circuit. But I'm concerned this may be hard since the FPGA is not well
specified for this sort of design.
Rick
Architecture of Minimal Delta Sigma Converters
Started by ●October 31, 2012
Reply by ●October 31, 20122012-10-31
On Wed, 31 Oct 2012 00:45:07 -0400, rickman wrote:> I am looking to use a delta sigma (DS) converter with a minimal > footprint in an FPGA, both in terms of LUT usage and power consumption. > Lattice Semiconductor has an app note on a design, but it is not much > like what I find described elsewhere. I'm not clear on how to analyze > this approach or how well it will work in my application. > > The main feature is that it uses the LVDS input as a comparator which I > believe equates to the quantizer in the various DS descriptions I have > read. I believe this comparator also combines the quantizer with a > summation of the input and the shaped error feedback. These papers also > include a dither input which is summed to the signal between the summed > input and the quantizer. Obviously if the input summation and the > quantizer are combined the dither can't be injected here. > > In fact, the error term is calculated by subtracting the summed input > from the quantized output. So this also can't be done. But then I'm > not sure exactly what this error term would be with a one bit > quantizer... I guess the input to the quantizer is intended to be > digital, but more than 1 bit.Not necessarily. The original sigma-delta concept was a one-bit quantizer and a one bit "DAC". The real divergence that I see is that they aren't integrating the error between the "DAC" output (Q of the first latch) and the input: instead they're low-passing the "DAC" output and comparing that to the input. _Something_ useful may result, but I'm not sure how much> > I'm having trouble picturing the DS conversions I see described in the > context of a circuit I can realize in the FPGA using the LVDS input as > the comparator. Am I not analyzing this correctly? > > The circuit Lattice describes is this... > |\ > input -->|+\ +----+ +------+ +--------+ > | >----|D Q|---+---|En Cnt|-----| Filter |---> Output > +--->|-/ | | | | | | | > | |/ |Clk | | |Clk | |Clk | > | +----+ | +------+ +--------+ > | | > +--------+--\/\/\-----+ > | R > = C > | > V > > The counter is allowed to run for some number of input samples and then > reset to give a decimation by N. This value is run through the IIR > filter and further decimated by M to produce the output samples. > > I'm sure this is far from an optimal design. But I can't really figure > out how to improve it given the limitations of using the LVDS input as a > comparator. > > Any suggestions? Any thoughts on how to analyze this?I'd try simulating it, first. It's so nonlinear that I don't think analysis will help much.> > I'm tempted to try to design an async circuit as a voltage to frequency > circuit. But I'm concerned this may be hard since the FPGA is not well > specified for this sort of design. >If you're going to play with the circuit, why not try the canonical sigma- delta topology? Integrate the difference between the latch output and your input, apply that to your LVDS, then filter that latch output. That'll give you a "true" sigma-delta, and then you major worry will be the accuracy and noise of the latch output. (Well, that and the fact that it's a 1st-order converter). This may help, even if it's about doing it in the other direction: http://www.embedded.com/design/configurable-systems/4006431/Sigma-delta- techniques-extend-DAC-resolution (or this: http://tinyurl.com/9dr5y5p) -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
Reply by ●October 31, 20122012-10-31
On 10/31/2012 3:59 PM, Tim Wescott wrote:> On Wed, 31 Oct 2012 00:45:07 -0400, rickman wrote: > >> I am looking to use a delta sigma (DS) converter with a minimal >> footprint in an FPGA, both in terms of LUT usage and power consumption. >> Lattice Semiconductor has an app note on a design, but it is not much >> like what I find described elsewhere. I'm not clear on how to analyze >> this approach or how well it will work in my application. >> >> The main feature is that it uses the LVDS input as a comparator which I >> believe equates to the quantizer in the various DS descriptions I have >> read. I believe this comparator also combines the quantizer with a >> summation of the input and the shaped error feedback. These papers also >> include a dither input which is summed to the signal between the summed >> input and the quantizer. Obviously if the input summation and the >> quantizer are combined the dither can't be injected here. >> >> In fact, the error term is calculated by subtracting the summed input >> from the quantized output. So this also can't be done. But then I'm >> not sure exactly what this error term would be with a one bit >> quantizer... I guess the input to the quantizer is intended to be >> digital, but more than 1 bit. > > Not necessarily. The original sigma-delta concept was a one-bit > quantizer and a one bit "DAC".What is the input to a one bit quantizer, analog, digital?> The real divergence that I see is that they aren't integrating the error > between the "DAC" output (Q of the first latch) and the input: instead > they're low-passing the "DAC" output and comparing that to the input.For small increments in the output an integrator and low pass filter with an appropriately long time constant are equivalent. Lattice recommends something greater than 200x the input sample rate.> _Something_ useful may result, but I'm not sure how much >> >> I'm having trouble picturing the DS conversions I see described in the >> context of a circuit I can realize in the FPGA using the LVDS input as >> the comparator. Am I not analyzing this correctly? >> >> The circuit Lattice describes is this... >> |\ >> input ---->|+\ +----+ +------+ +--------+ >> | >----|D Q|---+---|En Cnt|-----| Filter |---> Output >> +--->|-/ | | | | | | | >> | |/ |Clk | | |Clk | |Clk | >> | +----+ | +------+ +--------+ >> | | >> +--------+--\/\/\-----+ >> | R >> = C >> | >> V >> >> The counter is allowed to run for some number of input samples and then >> reset to give a decimation by N. This value is run through the IIR >> filter and further decimated by M to produce the output samples. >> >> I'm sure this is far from an optimal design. But I can't really figure >> out how to improve it given the limitations of using the LVDS input as a >> comparator. >> >> Any suggestions? Any thoughts on how to analyze this? > > I'd try simulating it, first. It's so nonlinear that I don't think > analysis will help much. >> >> I'm tempted to try to design an async circuit as a voltage to frequency >> circuit. But I'm concerned this may be hard since the FPGA is not well >> specified for this sort of design. >> > > If you're going to play with the circuit, why not try the canonical sigma- > delta topology? Integrate the difference between the latch output and > your input, apply that to your LVDS, then filter that latch output. > That'll give you a "true" sigma-delta, and then you major worry will be > the accuracy and noise of the latch output.How is that like the canonical DS topology? There is no dither and the error term isn't calculated the same. That's what I'm having trouble with, seeing the standard DS circuit in light of using the LVDS input as the comparitor/quantizer.> (Well, that and the fact that it's a 1st-order converter). > > This may help, even if it's about doing it in the other direction: > > http://www.embedded.com/design/configurable-systems/4006431/Sigma-delta- > techniques-extend-DAC-resolution > > (or this: http://tinyurl.com/9dr5y5p) >I think I've seen this one. That was by you, right? Rick
Reply by ●October 31, 20122012-10-31
On Wed, 31 Oct 2012 16:27:42 -0400, rickman wrote:> On 10/31/2012 3:59 PM, Tim Wescott wrote: >> On Wed, 31 Oct 2012 00:45:07 -0400, rickman wrote: >><snip>>> Not necessarily. The original sigma-delta concept was a one-bit >> quantizer and a one bit "DAC". > > What is the input to a one bit quantizer, analog, digital? >Analog <snip>>> If you're going to play with the circuit, why not try the canonical >> sigma- delta topology? Integrate the difference between the latch >> output and your input, apply that to your LVDS, then filter that latch >> output. That'll give you a "true" sigma-delta, and then you major worry >> will be the accuracy and noise of the latch output. > > How is that like the canonical DS topology? There is no dither and the > error term isn't calculated the same. That's what I'm having trouble > with, seeing the standard DS circuit in light of using the LVDS input as > the comparitor/quantizer.The canonical sigma-delta (or delta-sigma) has no explicit dither added to the analog signal: it just integrates the error between the digitized signal and the analog signal, and makes the digital signal out of that. Some sigma-delta converters do add some explicit dither, because by itself a sigma-delta converter is prone to oscillating at a specific (input dependent) frequency; humans being what we are, we pick up that highly-autocorrelated "noise" much better than we do white noise. So you add in some random dither to break up the tones, and the result sounds better. It might help to know what you're trying to do. If you're going for high quality audio, you're probably barking up the wrong tree. -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.com
Reply by ●November 1, 20122012-11-01
On 10/31/2012 5:29 PM, Tim Wescott wrote:> On Wed, 31 Oct 2012 16:27:42 -0400, rickman wrote: > >> On 10/31/2012 3:59 PM, Tim Wescott wrote: >>> On Wed, 31 Oct 2012 00:45:07 -0400, rickman wrote: >>> > <snip> > >>> Not necessarily. The original sigma-delta concept was a one-bit >>> quantizer and a one bit "DAC". >> >> What is the input to a one bit quantizer, analog, digital? >> > Analog > > <snip> > >>> If you're going to play with the circuit, why not try the canonical >>> sigma- delta topology? Integrate the difference between the latch >>> output and your input, apply that to your LVDS, then filter that latch >>> output. That'll give you a "true" sigma-delta, and then you major worry >>> will be the accuracy and noise of the latch output. >> >> How is that like the canonical DS topology? There is no dither and the >> error term isn't calculated the same. That's what I'm having trouble >> with, seeing the standard DS circuit in light of using the LVDS input as >> the comparitor/quantizer. > > The canonical sigma-delta (or delta-sigma) has no explicit dither added > to the analog signal: it just integrates the error between the digitized > signal and the analog signal, and makes the digital signal out of that.Ok, how do you get the error between the analog and the digital signals? That can't be done digitally because it would require the input signal to be digital, if I had that I wouldn't be using an ADC. lol> Some sigma-delta converters do add some explicit dither, because by > itself a sigma-delta converter is prone to oscillating at a specific > (input dependent) frequency; humans being what we are, we pick up that > highly-autocorrelated "noise" much better than we do white noise. So you > add in some random dither to break up the tones, and the result sounds > better. > > It might help to know what you're trying to do. If you're going for high > quality audio, you're probably barking up the wrong tree.No, not high quality audio. This will be an RF input from an antenna, but no, I'm not trying to build a one chip receiver... well, actually I am, but not for high RF, this is WWVB at 60 kHz. I need to detect either... the amplitude modulation or the phase modulation. They are transmitting both currently. They make it sound like phase modulation can be detected at lower signal levels which is an issue for this signal, at least on the east coast. With ~1 second integration time, I don't know that it will take a lot of SNR. In fact it may be possible to pull the signal out of the noise with a negative ratio. One idea is to sample synchronously at 240 kHz and work with a one bit signal. Rick
Reply by ●November 1, 20122012-11-01
On Thu, 01 Nov 2012 13:23:01 -0400, rickman wrote:> On 10/31/2012 5:29 PM, Tim Wescott wrote: >> On Wed, 31 Oct 2012 16:27:42 -0400, rickman wrote: >> >>> On 10/31/2012 3:59 PM, Tim Wescott wrote: >>>> On Wed, 31 Oct 2012 00:45:07 -0400, rickman wrote: >>>> >> <snip> >> >>>> Not necessarily. The original sigma-delta concept was a one-bit >>>> quantizer and a one bit "DAC". >>> >>> What is the input to a one bit quantizer, analog, digital? >>> >> Analog >> >> <snip> >> >>>> If you're going to play with the circuit, why not try the canonical >>>> sigma- delta topology? Integrate the difference between the latch >>>> output and your input, apply that to your LVDS, then filter that >>>> latch output. That'll give you a "true" sigma-delta, and then you >>>> major worry will be the accuracy and noise of the latch output. >>> >>> How is that like the canonical DS topology? There is no dither and >>> the error term isn't calculated the same. That's what I'm having >>> trouble with, seeing the standard DS circuit in light of using the >>> LVDS input as the comparitor/quantizer. >> >> The canonical sigma-delta (or delta-sigma) has no explicit dither added >> to the analog signal: it just integrates the error between the >> digitized signal and the analog signal, and makes the digital signal >> out of that. > > Ok, how do you get the error between the analog and the digital signals? > That can't be done digitally because it would require the input signal > to be digital, if I had that I wouldn't be using an ADC. lolThe way you get the error between the analog and digital signals is you convert the digital signal back to analog, via the latch output. Yes, it's only a two-state analog signal, but it's a voltage, it's in the analog domain, and you can subtract it from the input and integrate the results. This means, if you think about it, that the accuracy of the converter rests, in great part, on the accuracy of that "digital" output pin being well behaved in an analog sort of way: that it goes to the same high and low voltages always, and that it does so, if not promptly, then at least equally fast in both directions so that the average value of the voltage on that pin truly reflects the average of the ones and zeros behind it, in the digital domain. That, and the accuracy of the summing junction and integrator are your biggest drivers.>> Some sigma-delta converters do add some explicit dither, because by >> itself a sigma-delta converter is prone to oscillating at a specific >> (input dependent) frequency; humans being what we are, we pick up that >> highly-autocorrelated "noise" much better than we do white noise. So >> you add in some random dither to break up the tones, and the result >> sounds better. >> >> It might help to know what you're trying to do. If you're going for >> high quality audio, you're probably barking up the wrong tree. > > No, not high quality audio. This will be an RF input from an antenna, > but no, I'm not trying to build a one chip receiver... well, actually I > am, but not for high RF, this is WWVB at 60 kHz. I need to detect > either... the amplitude modulation or the phase modulation. They are > transmitting both currently. They make it sound like phase modulation > can be detected at lower signal levels which is an issue for this > signal, at least on the east coast.If you want to get wacky, use a zero-damping 60kHz bandpass filter instead of an integrator. I've seen papers on bandpass sigma-delta converters: the idea is that with a bandpass filter instead of an integrator, you have zero noise at your bandpass frequency instead of at DC. I rather suspect that the gain isn't worth the effort, particularly if the converter is sampling way faster than 60kHz (no, I couldn't tell you how much is "way faster" -- certainly 100x, probably not 10x, but exactly where to draw the line I couldn't tell you without putting real work into it).> With ~1 second integration time, I don't know that it will take a lot of > SNR. In fact it may be possible to pull the signal out of the noise > with a negative ratio.SNR is a pretty slippery definition in this case. You won't detect the signal unless the ratio is positive after your one second long boxcar filter -- the signal may be down in the mud at whatever your antenna bandwidth may be, but it has to be above noise in the 1Hz bandwidth you'll be measuring it at. I much prefer Eb/N0 ratios, as it is a figure that does not change with changing signal bandwidths.> One idea is to sample synchronously at 240 kHz and work with a one bit > signal.I don't think that'll work for you unless you've got some pretty good preamplification and filtering before the ADC. One bit sampling may work for you, but only if you filter well enough to not let your signal be drowned out by adjacent ones, and only if you sample fast enough to get enough coding gain to compensate for the random dither as opposed to the spectrally shaped dither you'd get from a sigma-delta. The app-note "sigma delta" converter may actually work in this case: it's really not a good converter at DC because they're "integrating" the wrong signal, but it may work OK at signals that are well off of zero frequency. I'd still use a "real" sigma-delta front end, unless one cruddy little op- amp and a handful of discrete components is really going to kill your space budget. (One op-amp, two caps, two resistors -- is that all that bad?) -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.com
Reply by ●November 1, 20122012-11-01
"rickman" <gnuarm@gmail.com> wrote in message news:k6ub5r$feb$1@dont-email.me...> On 10/31/2012 5:29 PM, Tim Wescott wrote:> No, not high quality audio. This will be an RF input from an antenna, but > no, I'm not trying to build a one chip receiver... well, actually I am, > but not for high RF, this is WWVB at 60 kHz. I need to detect either... > the amplitude modulation or the phase modulation. They are transmitting > both currently. They make it sound like phase modulation can be detected > at lower signal levels which is an issue for this signal, at least on the > east coast. > > With ~1 second integration time, I don't know that it will take a lot of > SNR. In fact it may be possible to pull the signal out of the noise with > a negative ratio. > > One idea is to sample synchronously at 240 kHz and work with a one bit > signal.Why throwing expensive FPGA at something that could be done with cheapish opamp and a PIC-class micro ? Vladimir Vassilevsky DSP and Mixed Signal Consultant www.abvolt.com
Reply by ●November 1, 20122012-11-01
On 11/1/2012 1:51 PM, Vladimir Vassilevsky wrote:> "rickman"<gnuarm@gmail.com> wrote in message > news:k6ub5r$feb$1@dont-email.me... >> On 10/31/2012 5:29 PM, Tim Wescott wrote: > >> No, not high quality audio. This will be an RF input from an antenna, but >> no, I'm not trying to build a one chip receiver... well, actually I am, >> but not for high RF, this is WWVB at 60 kHz. I need to detect either... >> the amplitude modulation or the phase modulation. They are transmitting >> both currently. They make it sound like phase modulation can be detected >> at lower signal levels which is an issue for this signal, at least on the >> east coast. >> >> With ~1 second integration time, I don't know that it will take a lot of >> SNR. In fact it may be possible to pull the signal out of the noise with >> a negative ratio. >> >> One idea is to sample synchronously at 240 kHz and work with a one bit >> signal. > > Why throwing expensive FPGA at something that could be done with cheapish > opamp and a PIC-class micro ?$3 is expensive? The problem is power. I am looking to do this in under 100 uA. At the rates I will be running the FPGA will be low 10's of uA. As long as I don't need any external circuits I expect it will meet that power budget. Rick
Reply by ●November 1, 20122012-11-01
On 11/1/2012 1:47 PM, Tim Wescott wrote:> On Thu, 01 Nov 2012 13:23:01 -0400, rickman wrote: >> >> Ok, how do you get the error between the analog and the digital signals? >> That can't be done digitally because it would require the input signal >> to be digital, if I had that I wouldn't be using an ADC. lol > > The way you get the error between the analog and digital signals is you > convert the digital signal back to analog, via the latch output. Yes, > it's only a two-state analog signal, but it's a voltage, it's in the > analog domain, and you can subtract it from the input and integrate the > results.Ok, so in the case with the LVDS input feeding a register, where would the integrator go? That is what I am not getting. How to use the LVDS in a sigma delta approach. If the integrator uses the registered signal as its input, isn't that what Lattice was doing with the counter?> This means, if you think about it, that the accuracy of the converter > rests, in great part, on the accuracy of that "digital" output pin being > well behaved in an analog sort of way: that it goes to the same high and > low voltages always, and that it does so, if not promptly, then at least > equally fast in both directions so that the average value of the voltage > on that pin truly reflects the average of the ones and zeros behind it, > in the digital domain. > > That, and the accuracy of the summing junction and integrator are your > biggest drivers.I will deal with accuracy after I figure out how this is supposed to work?>> No, not high quality audio. This will be an RF input from an antenna, >> but no, I'm not trying to build a one chip receiver... well, actually I >> am, but not for high RF, this is WWVB at 60 kHz. I need to detect >> either... the amplitude modulation or the phase modulation. They are >> transmitting both currently. They make it sound like phase modulation >> can be detected at lower signal levels which is an issue for this >> signal, at least on the east coast. > > If you want to get wacky, use a zero-damping 60kHz bandpass filter > instead of an integrator. I've seen papers on bandpass sigma-delta > converters: the idea is that with a bandpass filter instead of an > integrator, you have zero noise at your bandpass frequency instead of at > DC. > > I rather suspect that the gain isn't worth the effort, particularly if > the converter is sampling way faster than 60kHz (no, I couldn't tell you > how much is "way faster" -- certainly 100x, probably not 10x, but exactly > where to draw the line I couldn't tell you without putting real work into > it). > >> With ~1 second integration time, I don't know that it will take a lot of >> SNR. In fact it may be possible to pull the signal out of the noise >> with a negative ratio.Actually, I would be integrating for a fraction of a second, say 100 ms. Still that's 6000 cycles.>> One idea is to sample synchronously at 240 kHz and work with a one bit >> signal. > > I don't think that'll work for you unless you've got some pretty good > preamplification and filtering before the ADC. One bit sampling may work > for you, but only if you filter well enough to not let your signal be > drowned out by adjacent ones, and only if you sample fast enough to get > enough coding gain to compensate for the random dither as opposed to the > spectrally shaped dither you'd get from a sigma-delta.High Q antenna which is essentially a tuned circuit at 60 kHz.> The app-note "sigma delta" converter may actually work in this case: it's > really not a good converter at DC because they're "integrating" the wrong > signal, but it may work OK at signals that are well off of zero frequency. > > I'd still use a "real" sigma-delta front end, unless one cruddy little op- > amp and a handful of discrete components is really going to kill your > space budget. (One op-amp, two caps, two resistors -- is that all that > bad?)Depends on the power consumption. I want to keep the total current under 100 uA and I'd like to keep it well under.. I haven't researched front ends yet, but I'll still need the same circuit in the FPGA. Rick
Reply by ●November 1, 20122012-11-01
On Thu, 01 Nov 2012 15:23:58 -0400, rickman wrote:> On 11/1/2012 1:47 PM, Tim Wescott wrote: >> On Thu, 01 Nov 2012 13:23:01 -0400, rickman wrote: >>> >>> Ok, how do you get the error between the analog and the digital >>> signals? >>> That can't be done digitally because it would require the input >>> signal >>> to be digital, if I had that I wouldn't be using an ADC. lol >> >> The way you get the error between the analog and digital signals is you >> convert the digital signal back to analog, via the latch output. Yes, >> it's only a two-state analog signal, but it's a voltage, it's in the >> analog domain, and you can subtract it from the input and integrate the >> results. > > Ok, so in the case with the LVDS input feeding a register, where would > the integrator go? That is what I am not getting. How to use the LVDS > in a sigma delta approach..--------------------------------o latch out | | ___ || '---|___|---o---||-------. | || | | | | | input ___ | |\ | o--------|___|---o--|-\ | | >------o-------o LVDS+ .--|+/ | |/ Vdd/2 | o----------------o--------------------o LVDS- (created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)> If the integrator uses the registered signal as its input, isn't that > what Lattice was doing with the counter?The integrator uses the _difference_ of the input signal and the latch as its input. That's _different_ from what Lattice is doing. (Well, OK, in my minimial-component version it's using the sum, and an inverting integrator: that just means that the output of the ADC will be inverted w.r.t the actual voltage. You can fix that easily enough).>> This means, if you think about it, that the accuracy of the converter >> rests, in great part, on the accuracy of that "digital" output pin >> being well behaved in an analog sort of way: that it goes to the same >> high and low voltages always, and that it does so, if not promptly, >> then at least equally fast in both directions so that the average value >> of the voltage on that pin truly reflects the average of the ones and >> zeros behind it, in the digital domain. >> >> That, and the accuracy of the summing junction and integrator are your >> biggest drivers. > > I will deal with accuracy after I figure out how this is supposed to > work? > > >>> No, not high quality audio. This will be an RF input from an antenna, >>> but no, I'm not trying to build a one chip receiver... well, actually >>> I am, but not for high RF, this is WWVB at 60 kHz. I need to detect >>> either... the amplitude modulation or the phase modulation. They are >>> transmitting both currently. They make it sound like phase modulation >>> can be detected at lower signal levels which is an issue for this >>> signal, at least on the east coast. >> >> If you want to get wacky, use a zero-damping 60kHz bandpass filter >> instead of an integrator. I've seen papers on bandpass sigma-delta >> converters: the idea is that with a bandpass filter instead of an >> integrator, you have zero noise at your bandpass frequency instead of >> at DC. >> >> I rather suspect that the gain isn't worth the effort, particularly if >> the converter is sampling way faster than 60kHz (no, I couldn't tell >> you how much is "way faster" -- certainly 100x, probably not 10x, but >> exactly where to draw the line I couldn't tell you without putting real >> work into it). >> >>> With ~1 second integration time, I don't know that it will take a lot >>> of SNR. In fact it may be possible to pull the signal out of the >>> noise with a negative ratio. > > Actually, I would be integrating for a fraction of a second, say 100 ms. > Still that's 6000 cycles.And a 10dB difference in post-filtering SNR.>>> One idea is to sample synchronously at 240 kHz and work with a one bit >>> signal. >> >> I don't think that'll work for you unless you've got some pretty good >> preamplification and filtering before the ADC. One bit sampling may >> work for you, but only if you filter well enough to not let your signal >> be drowned out by adjacent ones, and only if you sample fast enough to >> get enough coding gain to compensate for the random dither as opposed >> to the spectrally shaped dither you'd get from a sigma-delta. > > High Q antenna which is essentially a tuned circuit at 60 kHz.If that's going to make sure you don't get any significant interference, then the random-dither approach may work.>> The app-note "sigma delta" converter may actually work in this case: >> it's really not a good converter at DC because they're "integrating" >> the wrong signal, but it may work OK at signals that are well off of >> zero frequency. >> >> I'd still use a "real" sigma-delta front end, unless one cruddy little >> op- amp and a handful of discrete components is really going to kill >> your space budget. (One op-amp, two caps, two resistors -- is that all >> that bad?) > > Depends on the power consumption. I want to keep the total current > under 100 uA and I'd like to keep it well under..There's low-power op-amps out there. Start digging.> I haven't researched front ends yet, but I'll still need the same > circuit in the FPGA. > > Rick-- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.com
