Discrete-time systems

Suppose you convert an analogue system with no time-delay to digital.
Say G(s) to G(z^-1) in backward shift format.
Intuitively, should the discrete-time version always have at least a 1 step delay
within it? ie can information travel from input to output instantaneously in the z-domain?

>> can information travel from input to output instantaneously in the
z-domain?

yes, the 0th power of z^-1 is 1. 

y = x is a valid z-domain equation, you'll find it from any textbook on
digital filters if you set all the other coefficients to zero.

In hardware, there is always a small physical delay, but you can merge
several of those during one sample period. 
That's the common synchronous logic design paradigm: combinatorial blocks
have a propagation delay, registers synchronize to the next clock cycle.

<gyansorova@gmail.com> wrote:
> Suppose you convert an analogue system with no time-delay to digital.
> Say G(s) to G(z^-1) in backward shift format.
> Intuitively, should the discrete-time version always have at least a 1 
> step delay
> within it? ie can information travel from input to output instantaneously 
> in the z-domain?

Here is the system for you H(z) = 1

On Nov 2, 10:38&#4294967295;am, "Vladimir Vassilevsky" <nos...@nowhere.com> wrote:
> <gyansor...@gmail.com> wrote:
> > Suppose you convert an analogue system with no time-delay to digital.
> > Say G(s) to G(z^-1) in backward shift format.
> > Intuitively, should the discrete-time version always have at least a 1
> > step delay
> > within it? ie can information travel from input to output instantaneously
> > in the z-domain?
>
> Here is the system for you H(z) = 1

On Friday, November 2, 2012 11:39:32 PM UTC+13, mnentwig wrote:
> >> can information travel from input to output instantaneously in the
> 
> z-domain?
> 
> 
> 
> yes, the 0th power of z^-1 is 1. 
> 
> 
> 
> y = x is a valid z-domain equation, you'll find it from any textbook on
> 
> digital filters if you set all the other coefficients to zero.
> 
> 
> 
> In hardware, there is always a small physical delay, but you can merge
> 
> several of those during one sample period. 
> 
> That's the common synchronous logic design paradigm: combinatorial blocks
> 
> have a propagation delay, registers synchronize to the next clock cycle.

Yes I know you'll find it in textbooks, but you know about them they are all either elementary, irrelevant or wrong.

suppose we have a digital control system, can the model of the system respond instantaneously? A computer surely must have a delay of one step as I pass data from input to output (unlike analogue). So you have a digital filter
which is say b0+b1z^-1+b2z^-2+... but when you IMPLEMENT it an extra delay must be there surely to get from input to output? No this doesn't matter for digital filters, who cares, but for controllers an extra delay is important - 

<gyansorova@gmail.com> wrote:

> Yes I know you'll find it in textbooks, but you know about them they are 
> all either elementary, irrelevant or wrong.

Can't read books. Too many letters.

> suppose we have a digital control system, can the model of the system 
> respond instantaneously? A computer surely must have a >delay of one step 
> as I pass data from input to output (unlike analogue). So you have a 
> digital filter
> which is say b0+b1z^-1+b2z^-2+... but when you IMPLEMENT it an extra delay 
> must be there surely to get from input to output? > No this doesn't matter 
> for digital filters, who cares, but for controllers an extra delay is 
> important -

Sample the input, do some calculation and output the result in femtosecond 
from input. No relevance to sample rate here.
However, if there is an asynchronous event at the input, it would be sampled 
after random delay of [0...1/Fsa). This makes for delay of 0.5/Fsa at 
average; and this is conceptual.

Vladimir Vassilevsky
DSP and Mixed Signal Consultant
www.abvolt.com

On Friday, November 2, 2012 10:14:49 PM UTC+13, gyans...@gmail.com wrote:
> Suppose you convert an analogue system with no time-delay to digital.
> 
> Say G(s) to G(z^-1) in backward shift format.
> 
> Intuitively, should the discrete-time version always have at least a 1 step delay
> 
> within it? ie can information travel from input to output instantaneously in the z-domain?
Your sample rate must be pretty fast if you can input and output data in a Femtosecond! Suppose the sampling rate was 1kHz then Ts = 1ms. So from input to output would be 1ms minimum. That data cannot travel instantaneously through the computer.

It's true you will always have a 1 sample delay minimum through any practical system but you can always just increase the sample rate assuming you have enough dsp horsepower to keep up. 

Bob

On 2012-11-02 21:48, gyansorova@gmail.com wrote:
[...]
> suppose we have a digital control system, can the model of the system respond instantaneously? A computer surely must have a delay of one step as I pass data from input to output (unlike analogue). So you have a digital filter
> which is say b0+b1z^-1+b2z^-2+... but when you IMPLEMENT it an extra delay must be there surely to get from input to output? No this doesn't matter for digital filters, who cares, but for controllers an extra delay is important - 

What makes you think analogue system do not have delay?

First of all, there is an upper limit, which is the speed
of "electrons" in circuit (far below the speed of light).
Second, you can always have a combination of analogue
components (LRC) causing a delay.

In the end, analogue delay lines do exist.

bye,

-- 

piergiorgio

>> but when you IMPLEMENT it an extra delay must be there surely to get
from input to output?

nope.
That's not for the filter, but the whole system.

Implement a single filter, then cascade 100 of them.
If I write the Verilog code, the resulting _system_ will have a latency of
_one sample_ (because I use one single register at the output to
synchronize the otherwise combinatorial path to the output clock.).

Now if anybody insists that implementing _the filter_ needs a delay (that
is, each of them!), you'd come out with a delay of 100 samples.