Discrete-time systems

"robert bristow-johnson" <rbj@audioimagination.com> wrote:
> On 11/3/12 9:29 PM, Vladimir Vassilevsky wrote:

>> Here is my point:  the conceptual delay in a sampled system is because 
>> you
>> can't get signal before input is sampled.

>> now, there are other situations like direct memory access (DMA) and 
>> sample
>> buffering (something i very recently gave a sorta crappy presentation
>> about and i think i'm gonna have to return to it next AES convention to
>> plug the holes).  those also affect delay. Vlad, i don't think it's a
>> STUPIDENT question.  these are exactly the kind of questions that should
>> be asked.
>
> Fie, boring and trivial shit.

> and necessary shit.  if one doesn't understand it, unhappy consequences 
> might result.

The one who doesn't understand this should first learn to walk on the back 
paws before getting into LTE PRACH channels.

>> Let's talk something more interesting. Like,
>> in PWM systems, the delay in feedback loop is variable due to the nature 
>> of
>> PWM.
>
> that (this particular nature of PWM) is also implementation specific. you 
> can do PWM where you advance the upward edge by half of the pulse width, 
> so that the center of the pulse is always at the same relative time.

To advance the leading edge, the signal has to be sampled before the PWM 
period starts. Which simply means designing the control system for the worst 
case delay, rather then optimal.

>> This makes optimal control a non-trivial problem.
> trivial is a subjective and relative thing.

Beauty and insignt are universal. So is shit and boredom.

VLV

robert bristow-johnson <rbj@audioimagination.com> wrote:

(snip, I wrote)

>> I presume also Vcc and GND. In that case, three wires more than needed.

>> http://en.wikipedia.org/wiki/1-Wire

>> (2 wires if you include ground.)
 
> i looked at the .pdf from the first-mentioned external link:
 
>    http://www.maximintegrated.com/products/1-wire/index.cfm?CMP=WP-7
 
> and it appears to be the "1-Wire", GND, and some "internal Vdd".  so 
> what i have understood to be the ostensible "3-wire interface" really 
> has at least 5 wires to include +5v or +3.3v and GND.  but, like other 
> digital circuits or with op-amps, i think the power supply is sorta 
> understood to be there, even when not indicated in the circuit.

The internal Vdd is a capacitor that is charged up when the 1-wire
is high. 
 
> that 1-wire wiki-thing referred to Dallas Semiconductor.  about a decade 
> ago, when or just before intel was supposedly putting serial numbers 
> into their pentiums, Dallas sold these little 3-wire thingies (that 
> looked like a transistor) where 2 of the wires were Vcc and GND.  

There is a three wire package, but only two are used.

Or a six wire package with only two used.

http://www.maximintegrated.com/datasheet/index.mvp/id/2903

> the 3rd wire was the I/O line, and must have been tri-state 
> (low-impedance 0, 1, and high impedance) which i presume the 
> serial interface (or a single bit from a parallel interface) 
> had to be also.
 
> this common "3-wire interface" is not even s'pose to be that.  just 
> serial bit data, bit clock, and word clock.  to the point of the 
> original question, it seems to me that *any* serial interface to a DAC 
> or ADC will have a delay of 1 sample (each) just to accommodate the 
> serial bit bottleneck.

-- glen

On 11/3/12 10:50 PM, Vladimir Vassilevsky wrote:
> "robert bristow-johnson"<rbj@audioimagination.com>  wrote:
>> On 11/3/12 9:29 PM, Vladimir Vassilevsky wrote:
>
>>> Here is my point:  the conceptual delay in a sampled system is because
>>> you
>>> can't get signal before input is sampled.
>
>>> now, there are other situations like direct memory access (DMA) and
>>> sample
>>> buffering (something i very recently gave a sorta crappy presentation
>>> about and i think i'm gonna have to return to it next AES convention to
>>> plug the holes).  those also affect delay. Vlad, i don't think it's a
>>> STUPIDENT question.  these are exactly the kind of questions that should
>>> be asked.
>>
>> Fie, boring and trivial shit.
>
>> and necessary shit.  if one doesn't understand it, unhappy consequences
>> might result.
>
> The one who doesn't understand this should first learn to walk on the back
> paws before getting into LTE PRACH channels.
>
>>> Let's talk something more interesting. Like,
>>> in PWM systems, the delay in feedback loop is variable due to the nature
>>> of PWM.
>>
>> that (this particular nature of PWM) is also implementation specific. you
>> can do PWM where you advance the upward edge by half of the pulse width,
>> so that the center of the pulse is always at the same relative time.
>
> To advance the leading edge, the signal has to be sampled before the PWM
> period starts. Which simply means designing the control system for the worst
> case delay, rather then optimal.

can't disagree with that.  (usually unnecessary and avoidable delay in a 
control loop is less than optimal.)

well, maybe i can disagree a little.  if your PWM range is limited (like 
it must be more than 30% duty cycle), then you can sorta start up the 
pulse edge 15% early and read in the input sample and decide then what 
to do about it.  but that's a detail.  in fact, maybe you can advance it 
to 30% and, if after reading the input sample you decide that the output 
PWM hits its minimum, you can shut it down right away.  just details. 
and from me, just speculation.  maybe this doesn't work.

i'm just picking on the letter of the content of what you say, Vlad. 
simply because, as i see it, you are sometimes being legalistic with 
language when convenient for you.  but you're less legalistic when it's 
not convenient.

it's sorta like when people complain when i say that the DFT, an 
inanimate *thing* (not a being who thinks), "assumes" a periodic 
extension.  could be couched better in technical and legalistic 
language.  but sometimes the anthropomorphic metaphor illustrates better 
than strict legalistic language.


>>> This makes optimal control a non-trivial problem.
>> trivial is a subjective and relative thing.
>
> Beauty and insight are universal.

dunno if that observation is shared universally.  i used to think it was 
true, but not enough people had the insight to what beauty really is (as 
i see it, being the authority on that matter), so i finally had to 
accept that it wasn't universal.

> So is shit and boredom.

ditto what i wrote above.  DSP math is boring (and also shit).  video 
games are not boring.  nothing boring in playing Grand Theft Auto all 
day, every day.

-- 

r b-j                  rbj@audioimagination.com

"Imagination is more important than knowledge."

On 11/3/12 10:53 PM, glen herrmannsfeldt wrote:
...
> The internal Vdd is a capacitor that is charged up when the 1-wire is high.

this is "high" from the output of the other device (supplying juice).  i 
guess the output better be reasonably low impedance (which is not so 
common for high).

and this two-terminal device better not require much juice.

and what happens when the output of the other device happens to not have 
many 1's in its output?  does this two-terminal get enough juice?

> There is a three wire package, but only two are used.
>
> Or a six wire package with only two used.
>
> http://www.maximintegrated.com/datasheet/index.mvp/id/2903

sounds like a sorta complicated "impedance".  even with silicon inside, 
it's a "passive" device.

still, the "3-wire interface" that is the common glueless connection of 
DSP to codec is: bit data, bit clock, word clock.

-- 

r b-j                  rbj@audioimagination.com

"Imagination is more important than knowledge."

On 2012-11-04 03:36, dbd wrote:
[...]
> The delay in analog circuits is the time until the electrons start moving according to the signal, not 'how long does it take electrons to get there'. This is the propagation time of the electric field not the electrons. Speed of light in a vacuum, less in matter, as glen measured.
[...]

You can define like that, but I guess satellite communication
might be more concerned with speed of light, as "delay".

bye,

-- 

piergiorgio

>> And if you use asynchronous logic, you'll not have even that one! :-)

simply use a DAC (output) clock phase that is slighly delayed, relative to
the ADC (input) sampling clock. 
Gives the output as fast as you can calculate it. Which is, instantaneous,
as far as my filter textbook equations are concerned.

As a sidenote:
They used to say, you can't solve Maxwell's equations for a CD player.
Well, probably nowadays you can :-) 
Anyway, they keep on trying.

The words 'discrete-time systems' and 'speed of light' belong to different
abstraction levels, say filter theory and hardware implementation. Mixing
them up without a very good reason is probably not a good idea, causes more
confusion than anything else. 

robert bristow-johnson <rbj@audioimagination.com> wrote:

(snip, I wrote)
>> The internal Vdd is a capacitor that is charged up when the 1-wire is high.
 
> this is "high" from the output of the other device (supplying juice).  i 
> guess the output better be reasonably low impedance (which is not so 
> common for high).

5K ohms to between 2.8V and 6.0V. Not so low.

http://datasheets.maximintegrated.com/en/ds/DS2401.pdf
 
> and this two-terminal device better not require much juice.
 
> and what happens when the output of the other device happens to not have 
> many 1's in its output?  does this two-terminal get enough juice?
 
>> There is a three wire package, but only two are used.

>> Or a six wire package with only two used.

>> http://www.maximintegrated.com/datasheet/index.mvp/id/2903
 
> sounds like a sorta complicated "impedance".  even with silicon inside, 
> it's a "passive" device.
 
> still, the "3-wire interface" that is the common glueless connection of 
> DSP to codec is: bit data, bit clock, word clock.

Somehow they get all that, and enough to power it, through 
that one wire.

-- glen

On Saturday, November 3, 2012 8:25:37 PM UTC-7, robert bristow-johnson wrote:
...
> 
> i'm just picking on the letter of the content of what you say, Vlad. 
> simply because, as i see it, you are sometimes being legalistic with 
> language when convenient for you.  but you're less legalistic when it's 
> not convenient.
> 
> it's sorta like when people complain when i say that the DFT, an 
> inanimate *thing* (not a being who thinks), "assumes" a periodic 
> extension.  could be couched better in technical and legalistic 
> language.  but sometimes the anthropomorphic metaphor illustrates better 
> than strict legalistic language.
> ...
> r b-j  

The difference is that Vlad chooses perspective as a matter of immediate convenience in legalistic discourse and the rb-j uses an anthropomorphic metaphor to deflect responsibility for the presumption of a restriction in perspective that can't be justified in technical language.

Dale B. Dalrymple

On 11/4/2012 10:37 AM, dbd wrote:
> On Saturday, November 3, 2012 8:25:37 PM UTC-7, robert bristow-johnson wrote:
> ...
>>
>> i'm just picking on the letter of the content of what you say, Vlad.
>> simply because, as i see it, you are sometimes being legalistic with
>> language when convenient for you.  but you're less legalistic when it's
>> not convenient.
>>
>> it's sorta like when people complain when i say that the DFT, an
>> inanimate *thing* (not a being who thinks), "assumes" a periodic
>> extension.  could be couched better in technical and legalistic
>> language.  but sometimes the anthropomorphic metaphor illustrates better
>> than strict legalistic language.
>> ...
>> r b-j
>
> The difference is that Vlad chooses perspective as a matter of immediate convenience in legalistic discourse and the rb-j uses an anthropomorphic metaphor to deflect responsibility for the presumption of a restriction in perspective that can't be justified in technical language.
>
> Dale B. Dalrymple

I'm sorry, techno-babble is not my first language.  Can you explain that 
in English?

Rick

On 11/4/2012 12:28 AM, robert bristow-johnson wrote:
> On 11/3/12 10:53 PM, glen herrmannsfeldt wrote:
> ...
>> The internal Vdd is a capacitor that is charged up when the 1-wire is
>> high.
>
> this is "high" from the output of the other device (supplying juice). i
> guess the output better be reasonably low impedance (which is not so
> common for high).
>
> and this two-terminal device better not require much juice.
>
> and what happens when the output of the other device happens to not have
> many 1's in its output? does this two-terminal get enough juice?

The controller output is actually an open drain and a resistor pulls up 
to Vdd.  The resistor is the "right" size to not require too much to 
pull it up and yet provide enough current to power the device(s) on the 
bus.

The protocol is pulse width modulated to provide timing info along with 
the data and to assure a minimum amount of '1' time to power the devices.

They are very simple devices.  There are some which are not so simple 
and require power.  The protocol is still 1-wire.


>> There is a three wire package, but only two are used.
>>
>> Or a six wire package with only two used.
>>
>> http://www.maximintegrated.com/datasheet/index.mvp/id/2903
>
> sounds like a sorta complicated "impedance". even with silicon inside,
> it's a "passive" device.
>
> still, the "3-wire interface" that is the common glueless connection of
> DSP to codec is: bit data, bit clock, word clock.
>

They also have a two pin package which is somewhere between a land grid 
array and a QFN, how do you call that one?  I think it might actually be 
"bump die" since it is just the silicon with no package around it IIRC.

Rick