Hi all, Sorry about starting another delta sigma modulator thread. I'm implementing a first order delta sigma DAC in a spare corner of an FPGA. It's for a low quality audio application. I'm driving a speaker differentially from two output pins. I'm using the regular "one liner" DSM code that produces a single output bit per clock. An output of 0 or 1 drives the two pins as 01 or 10 respectively to give a negative or positive voltage across the speaker. This should meet my requirements as is and it is currently simulating fine in Modelsim. However, I can actually get three levels out of the DAC: negative, positive and zero. I get zero from putting 00 or 11 on the pins. My gut feeling is that three levels should be better than two. Question: Can I get any improvement in quality by using a third level? How easy is it to use? Any links or references? Regards, Allan
Multi-level Delta Sigma DAC question
Started by ●November 2, 2012
Reply by ●November 2, 20122012-11-02
On Nov 2, 10:42�am, Allan Herriman <allanherri...@hotmail.com> wrote:> Hi all, > > Sorry about starting another delta sigma modulator thread. > > I'm implementing a first order delta sigma DAC in a spare corner of an > FPGA. �It's for a low quality audio application. > > I'm driving a speaker differentially from two output pins. > > I'm using the regular "one liner" DSM code that produces a single output > bit per clock. �An output of 0 or 1 drives the two pins as 01 or 10 > respectively to give a negative or positive voltage across the speaker. > > This should meet my requirements as is and it is currently simulating > fine in Modelsim. > > However, I can actually get three levels out of the DAC: negative, > positive and zero. �I get zero from putting 00 or 11 on the pins. > My gut feeling is that three levels should be better than two. > > Question: �Can I get any improvement in quality by using a third level? > How easy is it to use? > Any links or references? > > Regards, > Allanthink I remember a TI headphone pwm driver that had as sorta differential output it wasn't just differential, instead it was split in positive and negative output so for positive one side was held low the other toggling, and opposite for negative seems similar to what you are suggesting and I think it should give you an extra bit -Lasse
Reply by ●November 2, 20122012-11-02
"Allan Herriman" <allanherriman@hotmail.com> wrote:> I'm implementing a first order delta sigma DAC in a spare corner of an > FPGA. It's for a low quality audio application. > I'm driving a speaker differentially from two output pins. > > I'm using the regular "one liner" DSM code that produces a single output > bit per clock. An output of 0 or 1 drives the two pins as 01 or 10 > respectively to give a negative or positive voltage across the speaker.Are you driving the speaker directly from pins, without amplifier?> However, I can actually get three levels out of the DAC: negative, > positive and zero. I get zero from putting 00 or 11 on the pins. > My gut feeling is that three levels should be better than two. > > Question: Can I get any improvement in quality by using a third level?Yes of course. There will be substantial improvement. The concept is straightforward, although the implementation in FPGA would be somewhat more involved. However: 1. With two bits and few analog components, you can have 4 levels of DSM. That would simplify the implementation as well. 2. I would use PWM rather then delta sigma. That would minimize switching. 3. Speaker is very reactive load. The assumption that speaker behaves like resistor is a big mistake. Vladimir Vassilevsky DSP and Mixed Signal Consultant www.abvolt.com
Reply by ●November 2, 20122012-11-02
On Nov 2, 3:59�pm, "Vladimir Vassilevsky" <nos...@nowhere.com> wrote:> "Allan Herriman" <allanherri...@hotmail.com> wrote: > > I'm implementing a first order delta sigma DAC in a spare corner of an > > FPGA. �It's for a low quality audio application. > > I'm driving a speaker differentially from two output pins. > > > I'm using the regular "one liner" DSM code that produces a single output > > bit per clock. �An output of 0 or 1 drives the two pins as 01 or 10 > > respectively to give a negative or positive voltage across the speaker. > > Are you driving the speaker directly from pins, without amplifier? > > > However, I can actually get three levels out of the DAC: negative, > > positive and zero. �I get zero from putting 00 or 11 on the pins. > > My gut feeling is that three levels should be better than two. > > > Question: �Can I get any improvement in quality by using a third level? > > Yes of course. There will be substantial improvement. The concept is > straightforward, although the implementation in FPGA would be somewhat more > involved. > > However: > > 1. With two bits and few analog components, you can have 4 levels of DSM. > That would simplify the implementation as well. > 2. I would use PWM rather then delta sigma. That would minimize switching. > 3. Speaker is very reactive load. The assumption that speaker behaves like > resistor is a big mistake. >I'd think that for something lowpoer like this where switching losses isn't a big issue you'd want to maximise switching to make the filtering out the "carrier" easier you can also combine dsm and pwm, implement the output of a multilevel dsm with pwm to maximise switching with pwm try bit reversing the counter -Lasse
Reply by ●November 2, 20122012-11-02
On 11/2/12 10:59 AM, Vladimir Vassilevsky wrote:> "Allan Herriman"<allanherriman@hotmail.com> wrote: > >> I'm implementing a first order delta sigma DAC in a spare corner of an >> FPGA. It's for a low quality audio application. >> I'm driving a speaker differentially from two output pins. >> >> I'm using the regular "one liner" DSM code that produces a single output >> bit per clock. An output of 0 or 1 drives the two pins as 01 or 10 >> respectively to give a negative or positive voltage across the speaker. > > Are you driving the speaker directly from pins, without amplifier? > >> However, I can actually get three levels out of the DAC: negative, >> positive and zero. I get zero from putting 00 or 11 on the pins. >> My gut feeling is that three levels should be better than two. >> >> Question: Can I get any improvement in quality by using a third level? > > Yes of course. There will be substantial improvement. The concept is > straightforward, although the implementation in FPGA would be somewhat more > involved. > > However: > > 1. With two bits and few analog components, you can have 4 levels of DSM. > That would simplify the implementation as well.one thing to keep in mind is that there is a qualitative difference between a 1-bit DAC and one with more than 1 bit. whether this DAC is for a DAC or whether it's in an ADC (in either case, this DAC is in the loop). a 1-bit DAC is always in saturation mode. so. ironically, the 1-bit sigma-delta DAC never really moves from a linear mode to a saturation mode. it's always in the same mode. for an N-bit DAC (N>1), the slope of the DAC staircase function is the ostensible gain of the DAC if you were to model the whole thing regarding noise shaping. for the 1-bit DAC you gotta do something different to understand and correctly model the gain of the DAC (it's a statistical result that depends on the p.d.f. of the input). -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge."
Reply by ●November 2, 20122012-11-02
On Friday, November 2, 2012 5:42:51 AM UTC-4, Allan Herriman wrote:> Hi all, > > > > Sorry about starting another delta sigma modulator thread. > > > > I'm implementing a first order delta sigma DAC in a spare corner of an > > FPGA. It's for a low quality audio application. > > > > I'm driving a speaker differentially from two output pins. > > > > I'm using the regular "one liner" DSM code that produces a single output > > bit per clock. An output of 0 or 1 drives the two pins as 01 or 10 > > respectively to give a negative or positive voltage across the speaker. > > > > This should meet my requirements as is and it is currently simulating > > fine in Modelsim. > > > > > > However, I can actually get three levels out of the DAC: negative, > > positive and zero. I get zero from putting 00 or 11 on the pins. > > My gut feeling is that three levels should be better than two. > > > > Question: Can I get any improvement in quality by using a third level? > > How easy is it to use? > > Any links or references? > > > > Regards, > > AllanYou should define what you mean by "low quality". Almost all commercial class-D amps for portable speakers use a 3-level technique. However, there are a large variety of analog impairments such as power-supply modulation and inter-symbol interference that are usually mitigated by using analog feedback. You could probably get about 40 to 50 dB performance using open-loop, maybe 60 dB if you worked at it, but to get much higher than this you will need analog feedback. Note that noise-shaped PWM works somewhat better than delta-sigma for open-loop outputs, but there are too many details to go into here.
Reply by ●November 2, 20122012-11-02
<radams2000@gmail.com> wrote:> > > I'm implementing a first order delta sigma DAC in a spare corner of an > FPGA. It's for a low quality audio application.Wow. It's a rare opportunity to meet a specialist in Class D. My pleasure.>Almost all commercial class-D amps for portable speakers use a 3-level >technique.That is what they call "filterless PWM" or "carrierless PWM". It is done for obvious reasons. For everything else equal, the distortion is higher then with classic 2-level PWM.> However, there are a large variety of analog impairments such as > power-supply modulation and inter-symbol interference > that are usually mitigated by using analog feedback. > You could probably get about 40 to 50 dB performance using open-loop, > maybe 60 dB if you worked at it, but to get much higher > than this you > will need analog feedback.Yes. And may be precompensation as well.> Note that noise-shaped PWM works somewhat better than delta-sigma for > open-loop outputs, but there are too many > details to go into here.??? DSM is linear modulation; PWM is nonlinear. Hence noise shaping for DSM is straightforward; whereas noise shaping for PWM is not so trivial. Vladimir Vassilevsky DSP and Mixed Signal Consultant www.abvolt.com
Reply by ●November 2, 20122012-11-02
On Friday, November 2, 2012 5:42:51 AM UTC-4, Allan Herriman wrote:> Hi all, > > > > Sorry about starting another delta sigma modulator thread. > > > > I'm implementing a first order delta sigma DAC in a spare corner of an > > FPGA. It's for a low quality audio application. > > > > I'm driving a speaker differentially from two output pins. > > > > I'm using the regular "one liner" DSM code that produces a single output > > bit per clock. An output of 0 or 1 drives the two pins as 01 or 10 > > respectively to give a negative or positive voltage across the speaker. > > > > This should meet my requirements as is and it is currently simulating > > fine in Modelsim. > > > > > > However, I can actually get three levels out of the DAC: negative, > > positive and zero. I get zero from putting 00 or 11 on the pins. > > My gut feeling is that three levels should be better than two. > > > > Question: Can I get any improvement in quality by using a third level? > > How easy is it to use? > > Any links or references? > > > > Regards, > > AllanI should be more specific; when I mentioned "noise-shaped PWM" I didn't mean to imply that you can wrap a noise-shaping loop around a pwm modulator (which is difficult due to the latency). What I meant was that in a digital PWM system, the number of available pulse-widths you can make is quantized and depends on the highest master-clock available, and to overcome this quantization you need some noise-shaping. As a crude example, if you wanted to make an output pulse that was 20.5 master-clocks wide, you could produce a series of pulses that alternated between 20 and 21 mclks in width. Of course the real noise-shaping used is higher-order, so you would not get this simple pattern, but you get the idea.
Reply by ●November 2, 20122012-11-02
On 11/2/2012 4:09 PM, radams2000@gmail.com wrote:> On Friday, November 2, 2012 5:42:51 AM UTC-4, Allan Herriman wrote: >> >> Question: Can I get any improvement in quality by using a third level? >> How easy is it to use? >> Any links or references? >> >> Regards, >> >> Allan > > I should be more specific; when I mentioned "noise-shaped PWM" I didn't mean to imply that you can wrap a noise-shaping loop around a pwm modulator (which is difficult due to the latency). What I meant was that in a digital PWM system, the number of available pulse-widths you can make is quantized and depends on the highest master-clock available, and to overcome this quantization you need some noise-shaping. As a crude example, if you wanted to make an output pulse that was 20.5 master-clocks wide, you could produce a series of pulses that alternated between 20 and 21 mclks in width. Of course the real noise-shaping used is higher-order, so you would not get this simple pattern, but you get the idea.I have seen PWM described in several places for DACs. I have not seen SDM described. Is SDM less used (or at least less talked about) because it requires feedback of the analog output? I would think this could be emulated in hardware with an integrator. But then I guess this would have to match the characteristics of the attached speaker. Am I on the wrong track? Rick
Reply by ●November 3, 20122012-11-03
