Direct Conversion Receiver

I am contemplating a direct conversion receiver architecture
(versus a single-conversion superhet) but have heard of issues
in such designs.

  1. They are susceptible to microphonics 

     http://www.arrl.org/files/file/Technology/tis/info/pdf/9208019.pdf

  Why?

  2. They are susceptible to DC offset. 

  Why?

My contemplated architecture will use a fast ADC at the front end to
capture the RF spectrum from DC to my highest frequency of interest,
then filter and decimate in an FPGA down to a usable baseband bandwidth.
In other words, no mixers! So I won't have to worry about images.

Any thoughts regarding this? 
-- 
Randy Yates
Digital Signal Labs
http://www.digitalsignallabs.com

On Tue, 06 Nov 2012 11:46:11 -0500, Randy Yates
<yates@digitalsignallabs.com> wrote:

>I am contemplating a direct conversion receiver architecture
>(versus a single-conversion superhet) but have heard of issues
>in such designs.
>
>  1. They are susceptible to microphonics 
>
>     http://www.arrl.org/files/file/Technology/tis/info/pdf/9208019.pdf
>
>  Why?

That depends on the rf implementation.   Designs I've worked with
didn't have this problem.

>  2. They are susceptible to DC offset. 
>
>  Why?

Because any LO bleed-through winds up at DC as a static DC offset in a
coherent system.

>My contemplated architecture will use a fast ADC at the front end to
>capture the RF spectrum from DC to my highest frequency of interest,
>then filter and decimate in an FPGA down to a usable baseband bandwidth.
>In other words, no mixers! So I won't have to worry about images.
>
>Any thoughts regarding this? 
>-- 
>Randy Yates
>Digital Signal Labs
>http://www.digitalsignallabs.com

What you just described isn't a direct-conversion system, but a
sampled-IF or super-Nyquist sampled-IF system.   If you do a mix to
baseband digitally, or there is no mix to baseband and you demodulate
a bandpass signal, you won't have the DC offset problem.


Eric Jacobsen
Anchor Hill Communications
http://www.anchorhill.com

>I am contemplating a direct conversion receiver architecture
>(versus a single-conversion superhet) but have heard of issues
>in such designs.
>
>  1. They are susceptible to microphonics 
>
>     http://www.arrl.org/files/file/Technology/tis/info/pdf/9208019.pdf
>
>  Why?
>
>  2. They are susceptible to DC offset. 
>
>  Why?
>
>My contemplated architecture will use a fast ADC at the front end to
>capture the RF spectrum from DC to my highest frequency of interest,
>then filter and decimate in an FPGA down to a usable baseband bandwidth.
>In other words, no mixers! So I won't have to worry about images.
>
>Any thoughts regarding this? 
>-- 
>Randy Yates
>Digital Signal Labs
>http://www.digitalsignallabs.com
>

You won't have to worry about problems 1 and 2 with architecture that you
describe.  However, if you do an I/Q direct conversion to DC, then you will
definitely have to worry about DC offset, firstly, as Eric mention, you
will get the LO leaking through.  Additionally you will have to make sure
that the I/Q paths leading up to the dual A/D are perfectly balanced or you
will get an inverted image of your signal directly below your intended
signal.  The best you can hope for might be 40 dB instantaneous dynamic
range, and that is only gotten by dynamically calibrating the two paths for
phase and gain balance.  There are many devices out there that operate from
HF to over 5 GHz that integrate all the necessary components.

-Doug

On Tuesday, November 6, 2012 9:46:12 AM UTC-7, Randy Yates wrote:
> I am contemplating a direct conversion receiver architecture (versus a single-conversion superhet) but have heard of issues in such designs. 1. They are susceptible to microphonics http://www.arrl.org/files/file/Technology/tis/info/pdf/9208019.pdf Why? 2. They are susceptible to DC offset. Why? My contemplated architecture will use a fast ADC at the front end to capture the RF spectrum from DC to my highest frequency of interest, then filter and decimate in an FPGA down to a usable baseband bandwidth. In other words, no mixers! So I won't have to worry about images. Any thoughts regarding this? -- Randy Yates Digital Signal Labs http://www.digitalsignallabs.com

To me, with modern technology, the main issues from such a setup is the ADC power/spurs. "Low power" high speed ADCs are on the order of Watts but typially have lots of architecture tradeoffs to acheive this power. As a result, you get interleaving and interpolating spurs that typically don't decrease with respect to input power. Alternatively, you're looking at ADCs with power consumption on the order of 10s of Watts or more.

eric.jacobsen@ieee.org (Eric Jacobsen) writes:

> On Tue, 06 Nov 2012 11:46:11 -0500, Randy Yates
> <yates@digitalsignallabs.com> wrote:
>
>>I am contemplating a direct conversion receiver architecture
>>(versus a single-conversion superhet) but have heard of issues
>>in such designs.
>>
>>  1. They are susceptible to microphonics 
>>
>>     http://www.arrl.org/files/file/Technology/tis/info/pdf/9208019.pdf
>>
>>  Why?
>
> That depends on the rf implementation.   Designs I've worked with
> didn't have this problem.
>
>>  2. They are susceptible to DC offset. 
>>
>>  Why?
>
> Because any LO bleed-through winds up at DC as a static DC offset in a
> coherent system.
>
>>My contemplated architecture will use a fast ADC at the front end to
>>capture the RF spectrum from DC to my highest frequency of interest,
>>then filter and decimate in an FPGA down to a usable baseband bandwidth.
>>In other words, no mixers! So I won't have to worry about images.
>>
>>Any thoughts regarding this? 
>>-- 
>>Randy Yates
>>Digital Signal Labs
>>http://www.digitalsignallabs.com
>
> What you just described isn't a direct-conversion system, but a
> sampled-IF or super-Nyquist sampled-IF system.  

Hi Eric,

Thanks for the feedback. 

What IF are you talking about? There is no IF in what I described. 

> If you do a mix to baseband digitally, or there is no mix to baseband
> and you demodulate a bandpass signal, you won't have the DC offset
> problem.

The latter. I was planning on complex bandpass filtering at the high
sample rate, then decimating. I'm choosing the initial (high) sample
rate so that my band lies centered at DC after decimation. So, no mixer!
-- 
Randy Yates
Digital Signal Labs
http://www.digitalsignallabs.com

Bryan <bryan.paul@gmail.com> writes:

> On Tuesday, November 6, 2012 9:46:12 AM UTC-7, Randy Yates wrote:
>> I am contemplating a direct conversion receiver architecture (versus
>> a single-conversion superhet) but have heard of issues in such
>> designs. 1. They are susceptible to microphonics
>> http://www.arrl.org/files/file/Technology/tis/info/pdf/9208019.pdf
>> Why? 2. They are susceptible to DC offset. Why? My contemplated
>> architecture will use a fast ADC at the front end to capture the RF
>> spectrum from DC to my highest frequency of interest, then filter
>> and decimate in an FPGA down to a usable baseband bandwidth. In
>> other words, no mixers! So I won't have to worry about images. Any
>> thoughts regarding this? -- Randy Yates Digital Signal Labs
>> http://www.digitalsignallabs.com
>
> To me, with modern technology, the main issues from such a setup is
> the ADC power/spurs. "Low power" high speed ADCs are on the order of
> Watts but typially have lots of architecture tradeoffs to acheive this
> power. As a result, you get interleaving and interpolating spurs that
> typically don't decrease with respect to input power. Alternatively,
> you're looking at ADCs with power consumption on the order of 10s of
> Watts or more.

Hi Bryan,

Thank you for your input.

I'm considering the TI ADC08D502. The SFDR (about -60 dB) actually looks
to be well below the quantization noise floor. 

Power consumption of a few watts is not an issue.
-- 
Randy Yates
Digital Signal Labs
http://www.digitalsignallabs.com

Hi,

I did a quick calculation: If I'd plug it straight to a terminated 50 ohms
antenna, I'd get fullscale with a ~3 dBm CW signal, and a noise figure of
48 dB.
Put 20 dB of gain in front of it and it clips at -17 dBm with 28 dB noise
figure. Which is still 20 dB too high for any self-respecting receiver, but
this depends on the application. The first number, tolerance to blockers,
may be already too bad when radio, TV, WLAN or cell phone towers are near.

Besides noise, linearity may be a problem - the DAC isn't perfect - and the
preamplifier makes it even worse. With a wide-band frontend, there is a
huge number of input tone combinations (adjacent channels, TV, whatever)
that can cause inter- or crossmodulation products.

Your clock and timing uncertainty need to be as clean as a local oscillator
in a conventional receiver. This alone often rules out the idea.

I suspect you'll be better off using ready-made RF frontend components and
then digitize at some IF after filtering.

On Tuesday, November 6, 2012 9:23:31 AM UTC-8, Randy Yates wrote:
> ...
> The latter. I was planning on complex bandpass filtering at the high
> sample rate, then decimating. I'm choosing the initial (high) sample
> rate so that my band lies centered at DC after decimation. So, no mixer!
> 
> Randy Yates

I your architecture, the anti-aliasing requirements on the complex bandpass force the narrowest transition band in the system to be achieved at the highest system sampling frequency. For a given transition band, the higher the sampling frequency, the more coefficients in the filter. When the output bandwidth is considerably less than the maximum input frequency, it is much more efficient to mix and then desample with a multistage low-pass implementation that satisfies the tightest transition band requirement at a reduced sample frequency (and reduced number of coefficients in the filter). That means smaller, lower power and cheaper FPGAs.

Also, when the center frequency and bandwidth change, your architecture may require a new sampling frequency, desampling ratio and filter design. That means reloading the FPGAs and supplying a variable frequency clock instead of a fixed frequency clock to the required accuracy and jitter specs.

People have been designing mixer/desampler architectures for good reasons.

Dale B. Dalrymple

"mnentwig" <24789@dsprelated> writes:

> Hi,
>
> I did a quick calculation: If I'd plug it straight to a terminated 50 ohms
> antenna, I'd get fullscale with a ~3 dBm CW signal, and a noise figure of
> 48 dB.
> Put 20 dB of gain in front of it and it clips at -17 dBm with 28 dB noise
> figure. Which is still 20 dB too high for any self-respecting receiver, but
> this depends on the application. The first number, tolerance to blockers,
> may be already too bad when radio, TV, WLAN or cell phone towers are
> near.

Perhaps I was too tunnel-visioned when I wrote my original query. I
didn't mean just stick the antenna into the ADC. 

I presumed you would have some sort of "sufficient" preselector filter.
I also presumed one would have a front-end gain element that established 
system noise figure (mainly) and enough gain to overcome the insertion
loss, and then quite a bit, of the preselector. Then possibly a signal
conditioning amp prior to the ADC (after the preselector).

> Besides noise, linearity may be a problem - the DAC isn't perfect - 

Did you mean ADC?

> and the preamplifier makes it even worse. With a wide-band frontend,
> there is a huge number of input tone combinations (adjacent channels,
> TV, whatever) that can cause inter- or crossmodulation products.

Isn't that true for either DC or superhet topology? One needs a preamp
either way.

> Your clock and timing uncertainty need to be as clean as a local oscillator
> in a conventional receiver. This alone often rules out the idea.

Why? Why not make the ADC clock as clean as an LO?

> I suspect you'll be better off using ready-made RF frontend components and
> then digitize at some IF after filtering.

Well the devil is in these details, I suspect.
-- 
Randy Yates
Digital Signal Labs
http://www.digitalsignallabs.com

dbd <dbd@ieee.org> writes:

> On Tuesday, November 6, 2012 9:23:31 AM UTC-8, Randy Yates wrote:
>> ...
>> The latter. I was planning on complex bandpass filtering at the high
>> sample rate, then decimating. I'm choosing the initial (high) sample
>> rate so that my band lies centered at DC after decimation. So, no mixer!
>> 
>> Randy Yates
>
> I your architecture, the anti-aliasing requirements on the complex
> bandpass force the narrowest transition band in the system to be
> achieved at the highest system sampling frequency. For a given
> transition band, the higher the sampling frequency, the more
> coefficients in the filter. When the output bandwidth is considerably
> less than the maximum input frequency, it is much more efficient to
> mix and then desample with a multistage low-pass implementation that
> satisfies the tightest transition band requirement at a reduced sample
> frequency (and reduced number of coefficients in the filter). That
> means smaller, lower power and cheaper FPGAs.

Dale,

Thanks for your input. I hear your point here, but I have a question on
one detail: did you mean "mix" in analog?

> Also, when the center frequency and bandwidth change, your
> architecture may require a new sampling frequency, desampling ratio
> and filter design. That means reloading the FPGAs and supplying a
> variable frequency clock instead of a fixed frequency clock to the
> required accuracy and jitter specs.

That's not going to happen. Sorta like expecting GPS satellite
frequencies to change.

> People have been designing mixer/desampler architectures for good
> reasons.

Perhaps so, but I'm not going to hang on to coat tails, i.e., I want to
see the issues and make the tradeoffs myself.
-- 
Randy Yates
Digital Signal Labs
http://www.digitalsignallabs.com