This part touts an LFO that runs at 12 kHz for low power applications. Why would using this clock result in lower power than using a full-speed DCO clock, actively running 12,000 / 16,000,000 of the time, and sleeping the rest? -- Randy Yates Digital Signal Labs http://www.digitalsignallabs.com
LFO and Low Power Modes on the MSP430
Started by ●November 7, 2012
Reply by ●November 7, 20122012-11-07
On 7 Nov., 21:13, Randy Yates <ya...@digitalsignallabs.com> wrote:> This part touts an LFO that runs at 12 kHz for low power applications. > Why would using this clock result in lower power than using a > full-speed DCO clock, actively running 12,000 / 16,000,000 of the > time, and sleeping the rest? > -- > Randy Yates > Digital Signal Labshttp://www.digitalsignallabs.comit is usually complicated to figure out exactly what is the lowest power approach sometimes you cannot use sleep and just need to run at slowest speed possible and running fast in short burst doesn't always result in savings because it takes(wasted) time and power to start the fast clock source and wait for it to be stable -Lasse
Reply by ●November 7, 20122012-11-07
"langwadt@fonz.dk" <langwadt@fonz.dk> writes:> On 7 Nov., 21:13, Randy Yates <ya...@digitalsignallabs.com> wrote: >> This part touts an LFO that runs at 12 kHz for low power applications. >> Why would using this clock result in lower power than using a >> full-speed DCO clock, actively running 12,000 / 16,000,000 of the >> time, and sleeping the rest? >> -- >> Randy Yates >> Digital Signal Labshttp://www.digitalsignallabs.com > > it is usually complicated to figure out exactly what is the lowest > power approach > > sometimes you cannot use sleep and just need to run at slowest > speed possible > > and running fast in short burst doesn't always result in savings > because it takes(wasted) time and power to start the fast clock > source and wait for it to be stableThanks Lasse. Good input. I also just realized that to operate at 16 MHz you need to raise Vcc, which increases the power consumption nonlinearly! You can only run to 6 MHz and stay at 1.8 V. But still, 12,000 / 6,000,000... -- Randy Yates Digital Signal Labs http://www.digitalsignallabs.com
Reply by ●November 7, 20122012-11-07
On Wed, 07 Nov 2012 17:05:43 -0500, Randy Yates <yates@digitalsignallabs.com> wrote:>"langwadt@fonz.dk" <langwadt@fonz.dk> writes: > >> On 7 Nov., 21:13, Randy Yates <ya...@digitalsignallabs.com> wrote: >>> This part touts an LFO that runs at 12 kHz for low power applications. >>> Why would using this clock result in lower power than using a >>> full-speed DCO clock, actively running 12,000 / 16,000,000 of the >>> time, and sleeping the rest? >>> -- >>> Randy Yates >>> Digital Signal Labshttp://www.digitalsignallabs.com >> >> it is usually complicated to figure out exactly what is the lowest >> power approach >> >> sometimes you cannot use sleep and just need to run at slowest >> speed possible >> >> and running fast in short burst doesn't always result in savings >> because it takes(wasted) time and power to start the fast clock >> source and wait for it to be stable > >Thanks Lasse. Good input. > >I also just realized that to operate at 16 MHz you need to >raise Vcc, which increases the power consumption nonlinearly! You can >only run to 6 MHz and stay at 1.8 V. > >But still, 12,000 / 6,000,000... >-- >Randy Yates >Digital Signal Labs >http://www.digitalsignallabs.comI seem to recall that for a lot of technologies the clock net and drivers are all significant power consumers, and every clock pulse edge is a power event in the clock nets. This alone means that reducing the clock rate will result in a linear decrease in power consumption. Clock enables to make circuits sleep don't help reduce that, only shutting off clock nets completely or reducing their frequency. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com
Reply by ●November 7, 20122012-11-07
On 8 Nov., 00:01, eric.jacob...@ieee.org (Eric Jacobsen) wrote:> On Wed, 07 Nov 2012 17:05:43 -0500, Randy Yates > > > > > > > > > > <ya...@digitalsignallabs.com> wrote: > >"langw...@fonz.dk" <langw...@fonz.dk> writes: > > >> On 7 Nov., 21:13, Randy Yates <ya...@digitalsignallabs.com> wrote: > >>> This part touts an LFO that runs at 12 kHz for low power applications. > >>> Why would using this clock result in lower power than using a > >>> full-speed DCO clock, actively running 12,000 / 16,000,000 of the > >>> time, and sleeping the rest? > >>> -- > >>> Randy Yates > >>> Digital Signal Labshttp://www.digitalsignallabs.com > > >> it is usually complicated to figure out exactly what is the lowest > >> power approach > > >> sometimes you cannot use sleep and just need to run at slowest > >> speed possible > > >> and running fast in short burst doesn't always result in savings > >> because it takes(wasted) time and power to start the fast clock > >> source and wait for it to be stable > > >Thanks Lasse. Good input. > > >I also just realized that to operate at 16 MHz you need to > >raise Vcc, which increases the power consumption nonlinearly! You can > >only run to 6 MHz and stay at 1.8 V. > > >But still, 12,000 / 6,000,000... > >-- > >Randy Yates > >Digital Signal Labs > >http://www.digitalsignallabs.com > > I seem to recall that for a lot of technologies the clock net and > drivers are all significant power consumers, and every clock pulse > edge is a power event in the clock nets. � This alone means that > reducing the clock rate will result in a linear decrease in power > consumption.but also in a linear increase in time needed to do the same work> > Clock enables to make circuits sleep don't help reduce that, only > shutting off clock nets completely or reducing their frequency.I would think that for something designed for low power clock enables with be generally be implemented as a clock gating -Lasse
Reply by ●November 7, 20122012-11-07
On Wed, 7 Nov 2012 15:21:21 -0800 (PST), "langwadt@fonz.dk" <langwadt@fonz.dk> wrote:>On 8 Nov., 00:01, eric.jacob...@ieee.org (Eric Jacobsen) wrote: >> On Wed, 07 Nov 2012 17:05:43 -0500, Randy Yates >> >> >> >> >> >> >> >> >> >> <ya...@digitalsignallabs.com> wrote: >> >"langw...@fonz.dk" <langw...@fonz.dk> writes: >> >> >> On 7 Nov., 21:13, Randy Yates <ya...@digitalsignallabs.com> wrote: >> >>> This part touts an LFO that runs at 12 kHz for low power applications= >. >> >>> Why would using this clock result in lower power than using a >> >>> full-speed DCO clock, actively running 12,000 / 16,000,000 of the >> >>> time, and sleeping the rest? >> >>> -- >> >>> Randy Yates >> >>> Digital Signal Labshttp://www.digitalsignallabs.com >> >> >> it is usually complicated to figure out exactly what is the lowest >> >> power approach >> >> >> sometimes you cannot use sleep and just need to run at slowest >> >> speed possible >> >> >> and running fast in short burst doesn't always result in savings >> >> because it takes(wasted) time and power to start the fast clock >> >> source and wait for it to be stable >> >> >Thanks Lasse. Good input. >> >> >I also just realized that to operate at 16 MHz you need to >> >raise Vcc, which increases the power consumption nonlinearly! You can >> >only run to 6 MHz and stay at 1.8 V. >> >> >But still, 12,000 / 6,000,000... >> >-- >> >Randy Yates >> >Digital Signal Labs >> >http://www.digitalsignallabs.com >> >> I seem to recall that for a lot of technologies the clock net and >> drivers are all significant power consumers, and every clock pulse >> edge is a power event in the clock nets. =A0 This alone means that >> reducing the clock rate will result in a linear decrease in power >> consumption. > >but also in a linear increase in time needed to do the same workAbsolutely. And I meant a linear decrease in the clock net power consumption.>> Clock enables to make circuits sleep don't help reduce that, only >> shutting off clock nets completely or reducing their frequency. > >I would think that for something designed for low power clock enables >with be generally be implemented as a clock gating > >-LasseI'd think so, too, but not all target technologies are designed specifically for low power, and some fabrication technologies don't support clock gating easily. It seems to be an issue often enough that it's a possible explanation for what Randy is seeing. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com
Reply by ●November 7, 20122012-11-07
On Wed, 07 Nov 2012 15:13:35 -0500, Randy Yates <yates@digitalsignallabs.com> wrote:>This part touts an LFO that runs at 12 kHz for low power applications. >Why would using this clock result in lower power than using a >full-speed DCO clock, actively running 12,000 / 16,000,000 of the >time, and sleeping the rest? >-- >Randy Yates >Digital Signal Labs >http://www.digitalsignallabs.comOk, I'm a moron, or I should've started out asking for better context of what you're talking about. From what I can glean, in the MIDI world, if this is the context of your question, LFOs are generally implemented as analog VCOs and DCOs may or may not be NCO based or may be a digitally-controlled free-running VCO. An analog LFO designed specifically for low power and low frequency could easily be optimized (I'd think) to consume less power than a 16M oscillator divided down, for some of the same reasons that a 16M clock tree will consume more power than a 12kHz clock tree. But maybe I'm still out in the weeds about what you meant. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com
Reply by ●November 7, 20122012-11-07
>This part touts an LFO that runs at 12 kHz for low power applications. >Why would using this clock result in lower power than using a >full-speed DCO clock, actively running 12,000 / 16,000,000 of the >time, and sleeping the rest? >-- >Randy Yates >Digital Signal Labs >http://www.digitalsignallabs.com >How are you going to run the fast clock in your short bursts if you don't have the slow clock to wake the machine up for each burst? Steve
Reply by ●November 7, 20122012-11-07
"Randy Yates" <yates@digitalsignallabs.com> wrote:> This part touts an LFO that runs at 12 kHz for low power applications. > Why would using this clock result in lower power than using a > full-speed DCO clock, actively running 12,000 / 16,000,000 of the > time, and sleeping the rest?To control duty cycle of DCO, LFO is required anyway. Plus additional overhead for wake/sleep. Vladimir Vassilevsky DSP and Mixed Signal Consultant www.abvolt.com
Reply by ●November 7, 20122012-11-07
eric.jacobsen@ieee.org (Eric Jacobsen) writes:> On Wed, 07 Nov 2012 15:13:35 -0500, Randy Yates > <yates@digitalsignallabs.com> wrote: > >>This part touts an LFO that runs at 12 kHz for low power applications. >>Why would using this clock result in lower power than using a >>full-speed DCO clock, actively running 12,000 / 16,000,000 of the >>time, and sleeping the rest? >>-- >>Randy Yates >>Digital Signal Labs >>http://www.digitalsignallabs.com > > Ok, I'm a moron, or I should've started out asking for better context > of what you're talking about. > > From what I can glean, in the MIDI world, if this is the context of > your question, LFOs are generally implemented as analog VCOs and DCOs > may or may not be NCO based or may be a digitally-controlled > free-running VCO.Ha! I did have an LFO, VCOs, VCAs, and VCFs in my Minimoog back in the 70s. But that's not what I was talking about.> An analog LFO designed specifically for low power and low frequency > could easily be optimized (I'd think) to consume less power than a 16M > oscillator divided down, for some of the same reasons that a 16M clock > tree will consume more power than a 12kHz clock tree.Yes, this is the realm I was asking, but I'm not getting you. Clock tree? Are you referring to the parts of the design only concerned with generating the clock? If so, why is the clock that important; I mean, isn't the rest of the chip address latches flipping, registers clocking, etc., going to account for much more of the current? -- Randy Yates Digital Signal Labs http://www.digitalsignallabs.com
