CIC Compensating filter

I'm designing a CIC filter to perform a hardware efficient downsample.
My application is a little bit different in that the downsample factor
isn't very large, we're just doing a CIC in order to save multiplies
in the FPGA. I'm running into problems with the compensating filter,
however.

So far I've looked at a paper that describes using and integrated
second order polynomial (ISOP) for the compensating filter. This also
takes up very few multiplies but it doesn't perform extremely well for
our situation. Maybe I'm trying to squeeze too narrow of a bandwidth
out of the CIC - it seems like it won't work as well as a simple low
pass filter then downsample.

But here's my question. I noticed that the filter design toolbox will
create an inverse sinc fir filter using constrained equiripple design
criteria. I don't have the filter design toolbox. What are some
sources I can look at to find out how to do it myself? Or does anyone
have other recommendations for compensating filters? Thanks, in
advance.

Eric C. wrote:

> ... here's my question. I noticed that the filter design toolbox will
> create an inverse sinc fir filter using constrained equiripple design
> criteria. I don't have the filter design toolbox. What are some
> sources I can look at to find out how to do it myself? Or does anyone
> have other recommendations for compensating filters? Thanks, in
> advance.

There are many sources. http://www.iowegian.com/ is one good one. It's
companion site, http://www.DSPguru.com/ may have useful ideas for you.

Jerry
-- 
"I view the progress of science as ... the slow erosion of the
  tendency to dichotomize."                    Barbara Smuts, U. Mich.
���������������������������������������������������������������������

Practically speaking, you need to restrict your passband to the region
where the uncorrected CIC is less than 6db difference from the corrected
signal.  Beyond that, your correction filter has too high an order, and
more importantly you are losing SNR as you amplify the signal attenuated
by the CIC's rolloff.  The narrower the portion of the CIC you keep, the
easier the compensation.  Note that normally, your final passband should
be a small fraction (certainly not more than about 25%) of the first null
frequency in the CIC response.

"Eric C." wrote:

> I'm designing a CIC filter to perform a hardware efficient downsample.
> My application is a little bit different in that the downsample factor
> isn't very large, we're just doing a CIC in order to save multiplies
> in the FPGA. I'm running into problems with the compensating filter,
> however.
>
> So far I've looked at a paper that describes using and integrated
> second order polynomial (ISOP) for the compensating filter. This also
> takes up very few multiplies but it doesn't perform extremely well for
> our situation. Maybe I'm trying to squeeze too narrow of a bandwidth
> out of the CIC - it seems like it won't work as well as a simple low
> pass filter then downsample.
>
> But here's my question. I noticed that the filter design toolbox will
> create an inverse sinc fir filter using constrained equiripple design
> criteria. I don't have the filter design toolbox. What are some
> sources I can look at to find out how to do it myself? Or does anyone
> have other recommendations for compensating filters? Thanks, in
> advance.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759