Forums

ADC Vs DAC

Started by santosh nath September 9, 2003
Hi all,

I am not very familiar with ADC or DAC design or present research in
these area.
Popular sigma-delta,Flash or successive appoximation ADC design
methods are matured(?). I guess same terminology(sigma delta etc.) 
holds good for DAC.

Desiner cum researcher talk about high resolution(dynamic range), high
speed
DAC and ADC using oversampling techniques over low resolution ADC/DAC.

I have two fundamental questions:

Is there a theoretical limit for resolution like Shanon's capacity
theorem?

On same CMOS technology which gives better resolution and speed DAC or
ADC-
I guess DAC? - Is there any intuitive/logical explanation for it?

Don't laugh if does not make any sense - I am new in DAC/ADC.

Regards,
Santosh
santosh nath wrote:
> Hi all, > > I am not very familiar with ADC or DAC design or present research in > these area. > Popular sigma-delta,Flash or successive appoximation ADC design > methods are matured(?). I guess same terminology(sigma delta etc.) > holds good for DAC. > > Desiner cum researcher talk about high resolution(dynamic range), high > speed > DAC and ADC using oversampling techniques over low resolution ADC/DAC. > > I have two fundamental questions: > > Is there a theoretical limit for resolution like Shanon's capacity > theorem? > > On same CMOS technology which gives better resolution and speed DAC or > ADC- > I guess DAC? - Is there any intuitive/logical explanation for it? > > Don't laugh if does not make any sense - I am new in DAC/ADC.
Many ADCs use iterative approaches to determine the correct value, with a DAC in the feedback path and a comparitor. It is this iteration that is slow. Don't assume that ADCs and DAC are "opposite" in implementation :-) DACs can be as simple as an R-2R ladder which are pretty much instant, and when an integrated design, can be pretty accurate. Ben -- I'm not just a number. To many, I'm known as a String...
Ben Pope wrote:
> > santosh nath wrote: > > Hi all, > > > > I am not very familiar with ADC or DAC design or present research in > > these area. > > Popular sigma-delta,Flash or successive appoximation ADC design > > methods are matured(?). I guess same terminology(sigma delta etc.) > > holds good for DAC. > > > > Desiner cum researcher talk about high resolution(dynamic range), high > > speed > > DAC and ADC using oversampling techniques over low resolution ADC/DAC. > > > > I have two fundamental questions: > > > > Is there a theoretical limit for resolution like Shanon's capacity > > theorem? > > > > On same CMOS technology which gives better resolution and speed DAC or > > ADC- > > I guess DAC? - Is there any intuitive/logical explanation for it? > > > > Don't laugh if does not make any sense - I am new in DAC/ADC. > > Many ADCs use iterative approaches to determine the correct value, with a > DAC in the feedback path and a comparitor. It is this iteration that is > slow. > > Don't assume that ADCs and DAC are "opposite" in implementation :-) > > DACs can be as simple as an R-2R ladder which are pretty much instant, and > when an integrated design, can be pretty accurate. > > Ben > -- > I'm not just a number. To many, I'm known as a String...
What kind of resolution limit can you imagine? I see transistor noise as a limit to how small a voltage or voltage difference that can be measured. If one can integrate for a while, one can "see through" some of the noise. There are trade-offs for speed and number of meaningful bits in another way, too. When a signal is digitized, the best one can do is capture its average value in some intrval. The shorter that the interval can be made, the more meaning the measurement has. Linearity is important. A 24-bit DAC or ADC can separate 8,000,000 from 8,000,001. There is no practical way to test those numbers for accuracy, but their difference can matter. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Jerry Avins wrote:
> What kind of resolution limit can you imagine? I see transistor noise > as a limit to how small a voltage or voltage difference that can be > measured. If one can integrate for a while, one can "see through" some > of the noise. There are trade-offs for speed and number of meaningful > bits in another way, too. When a signal is digitized, the best one can > do is capture its average value in some intrval. The shorter that the > interval can be made, the more meaning the measurement has. > > Linearity is important. A 24-bit DAC or ADC can separate 8,000,000 > from 8,000,001. There is no practical way to test those numbers for > accuracy, but their difference can matter.
Jerry - it always worries me when you reply to my posts... I'm not clever enough! (and you usually have a good idea of the answer before hand) :-P I know you like to pose challenges - just look at your first question. :-) I have no idea what sort of resolution limit can be achieved, I suspect that there are a number of factors involved, many of which I cannot begin quantify. For this reason I like to stick to purely digital circuits, at low frequencies - especially when surrounded by people of far greater experience than myself. Thank you :-P Ben -- I'm not just a number. To many, I'm known as a String...

santosh nath wrote:
> > Hi all, > > I have two fundamental questions: > > Is there a theoretical limit for resolution like Shanon's capacity > theorem?
There is quantum noise limit on low end. Don't worry - it is very far from today's performance.
> On same CMOS technology which gives better resolution and speed DAC or > ADC- > I guess DAC? - Is there any intuitive/logical explanation for it?
Fast ADCs are "better" then fast DACs, because flash ADC settles faster then resistor - switch ladder. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
santosh.nath@ntlworld.com (santosh nath) wrote in message news:<6afd943a.0309090800.5499a0c3@posting.google.com>...
> Hi all, > > I am not very familiar with ADC or DAC design or present research in > these area. > Popular sigma-delta,Flash or successive appoximation ADC design > methods are matured(?). I guess same terminology(sigma delta etc.) > holds good for DAC. > > Desiner cum researcher talk about high resolution(dynamic range), high > speed > DAC and ADC using oversampling techniques over low resolution ADC/DAC. > > I have two fundamental questions: > > Is there a theoretical limit for resolution like Shanon's capacity > theorem?
Like anything else in sensitive electronics - if nothing else limits you, kTB will. If a converter is built in a bulk CMOS process, and you want it fast, you must use a leading edge fine process. That means your maximum voltage is rather limited. At the lower end kTB constrains what you can achieve. Between those is your potential dynamic range. Of course, bulk CMOS processes are not the quietest processes, so they don't get too close to the kTB limit. Customised processing can do better, but then you need you own fab. The market for such devices is fairly small. That makes them a specialist field - i.e. expensive.
> On same CMOS technology which gives better resolution and speed DAC or > ADC- > I guess DAC? - Is there any intuitive/logical explanation for it?
DACs glitch at the transitions. Most give a staircase output, before the restoration filter, so their response goes down the sinc at high frequencies :-). Various non-linearities cause a mass of spectral spurs, which are often a key performance limiter in RF applications. Bottom line: DACs have problems. Flash ADCs can settle damned fast these days, beating DACs on raw speed. The word widths are growing quite well, too. However, even if they are monolithic, performance varies somewhat with temperature, as the various parts of the chip do not track each other perfectly. IM products are usually much worse than their specs appear to show. Trying to keep the digital noise out of the analogue parts is also not easy. Bottom line: ADCs have problems. Just as tough as making a fast ADC or DAC is trying to clock the thing well. The tolerable jitter aperture on a fast and wide converter is incredibly small. That calls for ultra low phase noise clocks, and very clean grounds. Bottom line: designing in ADCs and DACs is a problem. If you want to do quadrature sampling, definitely look for a dual converter or the two channels will not track well as the temperature changes. Even then don't expect perfect tracking over a wide temperature range. This problem is even worse if you try to use multiple slower converters in a polyphase arrangement to get higher speed. Getting the clocking right for that is also a nightmare, as the acceptable jitter relates to the overall sampling rate. Designing ADCs and DACs is a black art. Only a few specialist groups do fast converters really well, and their successes are often more by luck than judgement. For example, in the early 90s, when commercial grade DDS chips, first appeared, so did DDS oriented DACs. However, those DACs all sucked. Everyone used a Sony DAC made for video in high end workstations. It wasn't designed for RF synthesis, but by luck it turned out to beat everything else hands down. So, do high end DACs or high end ADCs achieve higher performance? That depends on what you performance criteria are. They are both a major problem to do well. Regards, Steve
santosh nath wrote:

> Hi all, > > I am not very familiar with ADC or DAC design or present research > in these area. > Popular sigma-delta,Flash or successive appoximation ADC design > methods are matured(?). I guess same terminology(sigma delta etc.) > holds good for DAC. > > Desiner cum researcher talk about high resolution(dynamic range), > high speed > DAC and ADC using oversampling techniques over low resolution > ADC/DAC. > > I have two fundamental questions: > > Is there a theoretical limit for resolution like Shanon's capacity > theorem? > > On same CMOS technology which gives better resolution and speed > DAC or ADC- > I guess DAC? - Is there any intuitive/logical explanation for it? > > Don't laugh if does not make any sense - I am new in DAC/ADC. > > Regards, > Santosh
Hi Santosh, let me just add this to the other posts: if you intend to implement any ADC or DAC circuitry, you'll find out, that theoretical limits are not so important. It's more important, which resolution and/or speed you can really make use of / get hold of. For both (ADC and DAC) you need a reference voltage (if it isn't built into the device). A few years I had to design a voltage reference with a temperature drift of less than 1ppm/K. Although technology has improved since, I bet that you're not quick enough to count the bits by which a 24bit-ADC value runs away if temperature changes even with best achievable references. It's the same with the DAC. But it depends. If you do audio processing, you're usually not interested in long term stability, so you can (almost) ignore this drift stuff. If it comes to DC measurements, it will certainly beat all other effects. If you don't work with DC, you might find it as 1/f noise, and have to fight it at the lower frequency end. At the higher frequency end, you might have to fight aliasing effects which has to do with analog filtering. Suddenly you have to think of availability/cost/quality of analog components which might limit you. Sigma-Delta converters reveal another effect: single tones at certain frequencies which may be 20dB over the noise level. They depend on the input signal and can be very ugly. And - don't forget that you want to do something with the digital signal - maybe filtering or so. I deal with 24bit signals and dynamic ranges up to 120dB. I found that it is rather difficult to do filtering even with a 32bit floating point processor, because every filter stage (or section) costs a bit or two. This might lead you to very slow 64bit (or more) calculation algorithms and thus, your DSP's processing speed will dominate. If you're only interested in the theoretical limits, just for fun or so, I want to challenge you: if you think of a pure sine signal mixed with noise. filtering it with a bandpass would reduce the noise level, but not the signal in band. filtering it with a steeper bandpass would reduce the noise level more, but again, not influence the signal in band. if the signal amplitude would be exactly at the quantum noise level, would filtering give a means to isolate it ? If yes, would this work for a signal below the quantum noise floor, too? Bernhard -- before sending to the above email-address: replace deadspam.com by foerstergroup.de
(Comments interspersed below).

"Steve Underwood" <steveu@coppice.org> wrote in message
news:80bddbd7.0309092203.1ef34c90@posting.google.com...
> santosh.nath@ntlworld.com (santosh nath) wrote in message
news:<6afd943a.0309090800.5499a0c3@posting.google.com>...
> > Hi all, > > > > I am not very familiar with ADC or DAC design or present research
in
> > these area. > > Popular sigma-delta,Flash or successive appoximation ADC design > > methods are matured(?). I guess same terminology(sigma delta etc.) > > holds good for DAC. > > > > Desiner cum researcher talk about high resolution(dynamic range),
high
> > speed > > DAC and ADC using oversampling techniques over low resolution
ADC/DAC.
> > > > I have two fundamental questions: > > > > Is there a theoretical limit for resolution like Shanon's capacity > > theorem? >
There is the quantising noise floor, which is 6N+1.7dB below full scale, spread over the Nyquist range. There is also the fundamental kTB limit.
> Like anything else in sensitive electronics - if nothing else limits > you, kTB will. If a converter is built in a bulk CMOS process, and
you
> want it fast, you must use a leading edge fine process. That means > your maximum voltage is rather limited. At the lower end kTB > constrains what you can achieve. Between those is your potential > dynamic range. Of course, bulk CMOS processes are not the quietest > processes, so they don't get too close to the kTB limit.
<snip> This turns out not to be all that true - google on MB86064.
> > > On same CMOS technology which gives better resolution and speed
DAC or
> > ADC- > > I guess DAC? - Is there any intuitive/logical explanation for it? > > DACs glitch at the transitions. Most give a staircase output, before > the restoration filter, so their response goes down the sinc at high > frequencies :-). Various non-linearities cause a mass of spectral > spurs, which are often a key performance limiter in RF applications. > Bottom line: DACs have problems.
Yes, DACs can glitch at transitions, but well designed ones by not very much, and this is not even a fundamental property.
> > Flash ADCs can settle damned fast these days, beating DACs on raw > speed. The word widths are growing quite well, too. However, even if > they are monolithic, performance varies somewhat with temperature,
as
> the various parts of the chip do not track each other perfectly. IM > products are usually much worse than their specs appear to show. > Trying to keep the digital noise out of the analogue parts is also
not
> easy. Bottom line: ADCs have problems. >
Have a look at the MB86064, and try and come up with an ADC that comes anywhere close on the combination of speed and resolution. <snip>
> > Regards, > Steve
Regards Ian