MIPS and cycle

Hi all,

Does anybody know the exact difference between the above two? It seems to me
they're used interchangeably in many ocassions.

Thanks a lot!

George

Hi all,

Does anybody know the exact difference between the above two? It seems to me
they're used interchangeably in many ocassions.

Thanks a lot!

George

George wrote:
> 
> Hi all,
> 
> Does anybody know the exact difference between the above two? It seems to me
> they're used interchangeably in many ocassions.
> 
> Thanks a lot!
> 
> George

Instructions-per-cycle isn't necessarily one. It is often unclear
whether "cycles" refers to clock ticks or to instruction cycles, also
not a universal constant.

Jerry
-- 
Engineering is the art of making what you want from things you can get.
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Mike Rosing <rosing@neurophys.wisc.edu> wrote in message news:<3F554845.3010607@neurophys.wisc.edu>...
> George wrote:
> > Hi all,
> > 
> > Does anybody know the exact difference between the above two? It seems to me
> > they're used interchangeably in many ocassions.
> 
> On some processors you get 1 instruction per cycle, some take 2 cycles per
> instruction and some take 4.  Some processors are pipelined so they can do
> 3 parts of instructions in 1 cycle, so they are reported as 1 instruction
> per cycle (when they really aren't).  Cycles are the number of clock pulses
> fed into a procssor.  MIPS is million instructions per second.  They are
> not always the same, and in many cases the total number of cycles to do
> something is a lot more useful than a MIPS rating.
> 
> Patience, persistence, truth,
> Dr. mike

On RISC type processors, you need multiple instructions to get
*anything* done, where a CISC machine may have used a single
instruction to do the same.  So as Dr Mike pointed out, you have to do
your measurement over a larger problem, in order to be able to make a
meaningful comparison between processors.

Basically, a RISC architecture machine can execute one (or more)
instructions each clock cycle.  This is sometimes called a 'hard
wired' instruction decoder, where everything required to be done to
perform an instruction is actually done on a single clock edge.

A CISC machine usually has micromachine inside it, which executes the
microsteps required to perform a single instruction - a processor
inside a processor. Consequently, a typical CISC machine needs more
than one cycle to perform one instruction, but this can be alleviated
through pipelining and other parallelizing techniques, causing the
whole RISC vs CISC thing to become very blurry.

Cheers,

Herman
http://www.AerospaceSoftware.com

In comp.dsp, "George" <georgepu@sympatico.ca> wrote:

>Hi all,
>
>Does anybody know the exact difference between the above two? It seems to me
>they're used interchangeably in many ocassions.

   DSP and other processor cores are driven by a "clock", a signal of
a fixed, steady frequency. Many modern DSP's (and many other 'plain'
processors) execute one instruction in one cycle of the clock (for
most instructions - some others may take several clock cycles). ISTR
some recent high-end ones execute two, or maybe even more, instruction
in one clock cycle. Most older microprocessors take several cycles to
execute one instruction.
   So an "instruction time" and a "clock cycle time" often take the
same time, so they are sometimes used interchangably.
   MIPS is an acronym for Millions of Instructions Per Second. If a
processor has a clock speed of 20 MHz and executes one instruction per
clock cycle, it then runs at 20 MIPS. If it runs at the same 20 MHz
but takes two instructions per clock cycle, it only runs at 10 MIPS.

>
>Thanks a lot!
>
>George
>
>

>>>>> "Herman" == Herman Oosthuysen <HermanZA8@netscape.net> writes:

    Herman> On RISC type processors, you need multiple instructions to
    Herman> get *anything* done, where a CISC machine may have used a

Well, that's a bit of an exaggeration.  Adding 2 numbers is a single
instruction. 

    Herman> Basically, a RISC architecture machine can execute one (or
    Herman> more) instructions each clock cycle.  This is sometimes
    Herman> called a 'hard wired' instruction decoder, where
    Herman> everything required to be done to perform an instruction
    Herman> is actually done on a single clock edge.

I think that's not really true anymore on any reasonably current RISC
machine.  They're all heavily pipelined these days, so you might have
a throughput of one instruction per cycle, but each instruction takes
several clock cycles.

Ray

"George" <georgepu@sympatico.ca> wrote in message
news:CfH5b.19667$su.466610@news20.bellglobal.com...

(snip)

MIPS: Meaningless Indicator of Processor Speed

Ben Bradley wrote:
> 
>    DSP and other processor cores are driven by a "clock", a signal of
> a fixed, steady frequency. Many modern DSP's (and many other 'plain'
> processors) execute one instruction in one cycle of the clock (for
> most instructions - some others may take several clock cycles). ISTR
> some recent high-end ones execute two, or maybe even more, instruction
> in one clock cycle. Most older microprocessors take several cycles to
> execute one instruction.
>    So an "instruction time" and a "clock cycle time" often take the
> same time, so they are sometimes used interchangably.
>    MIPS is an acronym for Millions of Instructions Per Second. If a
> processor has a clock speed of 20 MHz and executes one instruction per
> clock cycle, it then runs at 20 MIPS. If it runs at the same 20 MHz
> but takes two instructions per clock cycle, it only runs at 10 MIPS.
> 

s/two instructions per clock cycle/two clock cycles per instruction/

Paul

In comp.dsp, Paul Russell <prussell@sonic.net> wrote:

>Ben Bradley wrote:
>> 
>>    DSP and other processor cores are driven by a "clock", a signal of
>> a fixed, steady frequency. Many modern DSP's (and many other 'plain'
>> processors) execute one instruction in one cycle of the clock (for
>> most instructions - some others may take several clock cycles). ISTR
>> some recent high-end ones execute two, or maybe even more, instruction
>> in one clock cycle. Most older microprocessors take several cycles to
>> execute one instruction.
>>    So an "instruction time" and a "clock cycle time" often take the
>> same time, so they are sometimes used interchangably.
>>    MIPS is an acronym for Millions of Instructions Per Second. If a
>> processor has a clock speed of 20 MHz and executes one instruction per
>> clock cycle, it then runs at 20 MIPS. If it runs at the same 20 MHz
>> but takes two instructions per clock cycle, it only runs at 10 MIPS.
>> 
>
>s/two instructions per clock cycle/two clock cycles per instruction/

   Yeah, what he said... [hangs head in shame over silly error]

>Paul
>

I agree with George. I've seen many times people using MIPS (often written 
MIPs - like they would be singular MIP and plural MIPS) to denote how much 
processing time a specific task would take. And worse, this MIPs is 
sometimes a fractional number! And oposed to the real meaning of MIPS 
(Million Instructions Per Second), the smaller it is, the better.

100 "MIPS" for a 300 MIPS processor, for example, it's supposed to be a 
third of the real-time cycle taken by the specific application. In a 
similar manner, 0.33 "MIPS" would like to tell 1 (the unit) is the whole 
processing time in a real-time cycle.

But all this is wrong and we should find another name instead of MIPs. Or 
maybe there is one and I don't know.

Adrian




George wrote:

> Hi all,
> 
> Does anybody know the exact difference between the above two? It seems to
> me they're used interchangeably in many ocassions.
> 
> Thanks a lot!
> 
> George

-- 
Adrian