DSPRelated.com
Forums

FFT in hw

Started by manishp June 16, 2013
Sirs,

Generally, when fft is imimplemented in hw, due to prohibitive silicon
area, the intermediate stages are allowed only 2 bit (for eg) growth. If I
simply see this from a mathematical perspective,  we do lose a very
significant amount of bits due to this. How come this is acceptable and
widely used in many hw fft implementation s?

Thanks, manish