Hi guys, i'm confused about conversion of numbers minus of zero to fixed point. I'm working in matlab with matrices (complex numbers), and some results are less than zero. When i do the fixed point analysis i use fi function and set word and fraction length until the algorithm works. But when i wrote with VHDL these result are almost equal to 1! I do a simple example: A= [ 120 +4500i; 1560 - 780i]; Adiv = [ 120 +4500i; 1560 - 780i]/ 4096 = [0.029+ 1.09i; 0.38 -0.19i]; A_fi = fi(A,1,13); Adiv_fi = fi(Adiv,1,8,6); Ok, when i implement this division in VHDL (shift), i see almost 1 or -1 or 0 for this numbers. I know i'm working in fixed point, but my method is right? I lost informations about decimals numbers?? How i do recover these?
Fixed Point Analysis and VHDL
Started by ●November 3, 2013
Reply by ●November 3, 20132013-11-03
On Monday, November 4, 2013 5:31:32 AM UTC+13, Ste_ee wrote:> Hi guys, i'm confused about conversion of numbers minus of zero to fixed point. > > > > I'm working in matlab with matrices (complex numbers), and some results are less than zero. > > When i do the fixed point analysis i use fi function and set word and fraction length until the algorithm works. But when i wrote with VHDL these result are almost equal to 1! > > I do a simple example: > > > > A= [ 120 +4500i; 1560 - 780i]; > > Adiv = [ 120 +4500i; 1560 - 780i]/ 4096 = [0.029+ 1.09i; 0.38 -0.19i]; > > > > A_fi = fi(A,1,13); > > Adiv_fi = fi(Adiv,1,8,6); > > > > Ok, when i implement this division in VHDL (shift), i see almost 1 or -1 or 0 for this numbers. I know i'm working in fixed point, but my method is right? > > I lost informations about decimals numbers?? How i do recover these?This post comes under the category Stupindo - your tutor Vlad will show you helpful comments in due time.
Reply by ●November 3, 20132013-11-03
Il giorno domenica 3 novembre 2013 17:47:14 UTC+1, gyans...@gmail.com ha scritto:> On Monday, November 4, 2013 5:31:32 AM UTC+13, Ste_ee wrote: > > > Hi guys, i'm confused about conversion of numbers minus of zero to fixed point. > > > > > > > > > > > > I'm working in matlab with matrices (complex numbers), and some results are less than zero. > > > > > > When i do the fixed point analysis i use fi function and set word and fraction length until the algorithm works. But when i wrote with VHDL these result are almost equal to 1! > > > > > > I do a simple example: > > > > > > > > > > > > A= [ 120 +4500i; 1560 - 780i]; > > > > > > Adiv = [ 120 +4500i; 1560 - 780i]/ 4096 = [0.029+ 1.09i; 0.38 -0.19i]; > > > > > > > > > > > > A_fi = fi(A,1,13); > > > > > > Adiv_fi = fi(Adiv,1,8,6); > > > > > > > > > > > > Ok, when i implement this division in VHDL (shift), i see almost 1 or -1 or 0 for this numbers. I know i'm working in fixed point, but my method is right? > > > > > > I lost informations about decimals numbers?? How i do recover these? > > > > This post comes under the category Stupindo - your tutor Vlad will show you helpful comments in due time.Do i have a tutor??????
Reply by ●November 3, 20132013-11-03
On Sun, 03 Nov 2013 08:31:32 -0800, Ste_ee wrote:> Hi guys, i'm confused about conversion of numbers minus of zero to fixed > point. > > I'm working in matlab with matrices (complex numbers), and some results > are less than zero. > When i do the fixed point analysis i use fi function and set word and > fraction length until the algorithm works. But when i wrote with VHDL > these result are almost equal to 1! > I do a simple example: > > A= [ 120 +4500i; 1560 - 780i]; > Adiv = [ 120 +4500i; 1560 - 780i]/ 4096 = [0.029+ 1.09i; 0.38 -0.19i]; > > A_fi = fi(A,1,13); > Adiv_fi = fi(Adiv,1,8,6); > > Ok, when i implement this division in VHDL (shift), i see almost 1 or -1 > or 0 for this numbers. I know i'm working in fixed point, but my method > is right? > I lost informations about decimals numbers?? How i do recover these?You are somehow misusing VHDL. Try to make an example that's just a few lines long and post that. Are you trying to keep things as fixed point, or integers, or what? Are you using some sort of a fixed point or fractional type in VHDL, or an integer type? If you're using integers -- how do you best represent 0.38 as an integer? -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
Reply by ●November 3, 20132013-11-03
Il giorno domenica 3 novembre 2013 19:46:48 UTC+1, Tim Wescott ha scritto:> On Sun, 03 Nov 2013 08:31:32 -0800, Ste_ee wrote: > > > > > Hi guys, i'm confused about conversion of numbers minus of zero to fixed > > > point. > > > > > > I'm working in matlab with matrices (complex numbers), and some results > > > are less than zero. > > > When i do the fixed point analysis i use fi function and set word and > > > fraction length until the algorithm works. But when i wrote with VHDL > > > these result are almost equal to 1! > > > I do a simple example: > > > > > > A= [ 120 +4500i; 1560 - 780i]; > > > Adiv = [ 120 +4500i; 1560 - 780i]/ 4096 = [0.029+ 1.09i; 0.38 -0.19i]; > > > > > > A_fi = fi(A,1,13); > > > Adiv_fi = fi(Adiv,1,8,6); > > > > > > Ok, when i implement this division in VHDL (shift), i see almost 1 or -1 > > > or 0 for this numbers. I know i'm working in fixed point, but my method > > > is right? > > > I lost informations about decimals numbers?? How i do recover these? > > > > You are somehow misusing VHDL. Try to make an example that's just a few > > lines long and post that. > > > > Are you trying to keep things as fixed point, or integers, or what? Are > > you using some sort of a fixed point or fractional type in VHDL, or an > > integer type? If you're using integers -- how do you best represent 0.38 > > as an integer? > > > > -- > > Tim Wescott > > Control system and signal processing consulting > > www.wescottdesign.comIn my VHDL i use std_logic_vector and i want represent fixed point example of the division by 4096 a11,a12,a21,a22 : in std_logic_vector(15 downto 0); b11,b12,b21,b22 : out std_logic_vector(9 downto 0); .... b11 = "000000" & a11(15 downto 12); -- all positive numbers b12 = "000000" & a12(15 downto 12); So i trunk the decimals, but i don't know... Thanks very much
Reply by ●November 3, 20132013-11-03
Il giorno domenica 3 novembre 2013 20:10:44 UTC+1, Ste_ee ha scritto:> Il giorno domenica 3 novembre 2013 19:46:48 UTC+1, Tim Wescott ha scritto: > > > On Sun, 03 Nov 2013 08:31:32 -0800, Ste_ee wrote: > > > > > > > > > > > > > Hi guys, i'm confused about conversion of numbers minus of zero to fixed > > > > > > > point. > > > > > > > > > > > > > > I'm working in matlab with matrices (complex numbers), and some results > > > > > > > are less than zero. > > > > > > > When i do the fixed point analysis i use fi function and set word and > > > > > > > fraction length until the algorithm works. But when i wrote with VHDL > > > > > > > these result are almost equal to 1! > > > > > > > I do a simple example: > > > > > > > > > > > > > > A= [ 120 +4500i; 1560 - 780i]; > > > > > > > Adiv = [ 120 +4500i; 1560 - 780i]/ 4096 = [0.029+ 1.09i; 0.38 -0.19i]; > > > > > > > > > > > > > > A_fi = fi(A,1,13); > > > > > > > Adiv_fi = fi(Adiv,1,8,6); > > > > > > > > > > > > > > Ok, when i implement this division in VHDL (shift), i see almost 1 or -1 > > > > > > > or 0 for this numbers. I know i'm working in fixed point, but my method > > > > > > > is right? > > > > > > > I lost informations about decimals numbers?? How i do recover these? > > > > > > > > > > > > You are somehow misusing VHDL. Try to make an example that's just a few > > > > > > lines long and post that. > > > > > > > > > > > > Are you trying to keep things as fixed point, or integers, or what? Are > > > > > > you using some sort of a fixed point or fractional type in VHDL, or an > > > > > > integer type? If you're using integers -- how do you best represent 0.38 > > > > > > as an integer? > > > > > > > > > > > > -- > > > > > > Tim Wescott > > > > > > Control system and signal processing consulting > > > > > > www.wescottdesign.com > > > > In my VHDL i use std_logic_vector and i want represent fixed point > > > > example of the division by 4096 > > > > a11,a12,a21,a22 : in std_logic_vector(15 downto 0); > > > > b11,b12,b21,b22 : out std_logic_vector(9 downto 0); > > > > .... > > > > b11 = "000000" & a11(15 downto 12); -- all positive numbers > > b12 = "000000" & a12(15 downto 12); > > > > So i trunk the decimals, but i don't know... > > Thanks very muchThe problem is this: I want manipulate numbers less than zero with fixed point representation in VHDL, using only std_logic_vector, if is possible..I wouldn't to use fixed_point packages like in vhdl.org.
Reply by ●November 3, 20132013-11-03
On Sun, 03 Nov 2013 12:14:44 -0800, Ste_ee wrote:> Il giorno domenica 3 novembre 2013 20:10:44 UTC+1, Ste_ee ha scritto: >> Il giorno domenica 3 novembre 2013 19:46:48 UTC+1, Tim Wescott ha >> scritto: >> >> > On Sun, 03 Nov 2013 08:31:32 -0800, Ste_ee wrote: >> >> >> > >> >> > >> >> > >> > > Hi guys, i'm confused about conversion of numbers minus of zero to >> > > fixed >> >> >> > >> > > point. >> >> >> > >> >> > > >> >> > >> > > I'm working in matlab with matrices (complex numbers), and some >> > > results >> >> >> > >> > > are less than zero. >> >> >> > >> > > When i do the fixed point analysis i use fi function and set word >> > > and >> >> >> > >> > > fraction length until the algorithm works. But when i wrote with >> > > VHDL >> >> >> > >> > > these result are almost equal to 1! >> >> >> > >> > > I do a simple example: >> >> >> > >> >> > > >> >> > >> > > A= [ 120 +4500i; 1560 - 780i]; >> >> >> > >> > > Adiv = [ 120 +4500i; 1560 - 780i]/ 4096 = [0.029+ 1.09i; 0.38 >> > > -0.19i]; >> >> >> > >> >> > > >> >> > >> > > A_fi = fi(A,1,13); >> >> >> > >> > > Adiv_fi = fi(Adiv,1,8,6); >> >> >> > >> >> > > >> >> > >> > > Ok, when i implement this division in VHDL (shift), i see almost 1 >> > > or -1 >> >> >> > >> > > or 0 for this numbers. I know i'm working in fixed point, but my >> > > method >> >> >> > >> > > is right? >> >> >> > >> > > I lost informations about decimals numbers?? How i do recover >> > > these? >> >> >> > >> >> > >> >> > >> > You are somehow misusing VHDL. Try to make an example that's just a >> > few >> >> >> > >> > lines long and post that. >> >> >> > >> >> > >> >> > >> > Are you trying to keep things as fixed point, or integers, or what? >> > Are >> >> >> > >> > you using some sort of a fixed point or fractional type in VHDL, or >> > an >> >> >> > >> > integer type? If you're using integers -- how do you best represent >> > 0.38 >> >> >> > >> > as an integer? >> >> >> > >> >> > >> >> > >> > -- >> >> >> > >> > Tim Wescott >> >> >> > >> > Control system and signal processing consulting >> >> >> > >> > www.wescottdesign.com >> >> >> >> In my VHDL i use std_logic_vector and i want represent fixed point >> >> >> >> example of the division by 4096 >> >> >> >> a11,a12,a21,a22 : in std_logic_vector(15 downto 0); >> >> >> >> b11,b12,b21,b22 : out std_logic_vector(9 downto 0); >> >> >> >> .... >> >> >> >> b11 = "000000" & a11(15 downto 12); -- all positive numbers >> >> b12 = "000000" & a12(15 downto 12); >> >> >> >> So i trunk the decimals, but i don't know... >> >> Thanks very much > > The problem is this: I want manipulate numbers less than zero with fixed > point representation in VHDL, using only std_logic_vector, if is > possible..I wouldn't to use fixed_point packages like in vhdl.org.I'm not sure about VHDL conventions, but if std_logic_vector translates into anything other than a set of bits, it translates into a fixed point integer. You're trying to deal with values that have significant meaning in the numbers to the right of the radix point. You need to choose a numerical representation that is consistent with that -- i.e., the weight of your LSB needs to be less than 1. Then you need to write your code to take that into account. What you'll find is that for additions and subtractions you don't change much, because the inputs and output bit weights are the same. But multiplies (and divides, if you do them) will be different. Basically, if you multiply two signed integers of width N, the complete answer will be of width 2N-1. Which N of those 2N-1 bits you choose as your "answer" is dictated by (or dictates, depending on your point of view) by the scaling that you've chosen for your data. So far, I don't see anything in your comments to indicate that you understand this point. If you don't get that, you won't get anywhere. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●November 4, 20132013-11-04
On Sun, 3 Nov 2013 08:31:32 -0800 (PST), Ste_ee <stefano.cap91@gmail.com> wrote:>Hi guys, i'm confused about conversion of numbers minus of zero to fixed point. > >I'm working in matlab with matrices (complex numbers), and some results are less than zero. >When i do the fixed point analysis i use fi function and set word and fraction length until the algorithm works. But when i wrote with VHDL these result are almost equal to 1! >I do a simple example: > >A= [ 120 +4500i; 1560 - 780i]; >Adiv = [ 120 +4500i; 1560 - 780i]/ 4096 = [0.029+ 1.09i; 0.38 -0.19i]; > >A_fi = fi(A,1,13); >Adiv_fi = fi(Adiv,1,8,6); > >Ok, when i implement this division in VHDL (shift), i see almost 1 or -1 or 0 for this numbers. I know i'm working in fixed point, but my method is right? >I lost informations about decimals numbers?? How i do recover these?First, do you understand two's complement binary arithmetic? Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com
Reply by ●November 4, 20132013-11-04
On Sun, 03 Nov 2013 12:14:44 -0800, Ste_ee wrote:> Il giorno domenica 3 novembre 2013 20:10:44 UTC+1, Ste_ee ha scritto: >> Il giorno domenica 3 novembre 2013 19:46:48 UTC+1, Tim Wescott ha >> scritto: >> >> > On Sun, 03 Nov 2013 08:31:32 -0800, Ste_ee wrote: >> >> >> > >> >> > >> >> > >> > > Hi guys, i'm confused about conversion of numbers minus of zero to >> > > fixed >> >> >> > >> > > point. >> >> >> > >> >> > > >> >> > >> > > I'm working in matlab with matrices (complex numbers), and some >> > > results >> >> >> > >> > > are less than zero. >> >> >> > >> > > When i do the fixed point analysis i use fi function and set word >> > > and >> >> >> > >> > > fraction length until the algorithm works. But when i wrote with >> > > VHDL >> >> >> > >> > > these result are almost equal to 1! >> >> >> > >> > > I do a simple example: >> >> >> > >> >> > > >> >> > >> > > A= [ 120 +4500i; 1560 - 780i]; >> >> >> > >> > > Adiv = [ 120 +4500i; 1560 - 780i]/ 4096 = [0.029+ 1.09i; 0.38 >> > > -0.19i]; >> >> >> > >> >> > > >> >> > >> > > A_fi = fi(A,1,13); >> >> >> > >> > > Adiv_fi = fi(Adiv,1,8,6); >> >> >> > >> >> > > >> >> > >> > > Ok, when i implement this division in VHDL (shift), i see almost 1 >> > > or -1 >> >> >> > >> > > or 0 for this numbers. I know i'm working in fixed point, but my >> > > method >> >> >> > >> > > is right? >> >> >> > >> > > I lost informations about decimals numbers?? How i do recover >> > > these? >> >> >> > >> >> > >> >> > >> > You are somehow misusing VHDL. Try to make an example that's just a >> > few >> >> >> > >> > lines long and post that. >> >> >> > >> >> > >> >> > >> > Are you trying to keep things as fixed point, or integers, or what? >> > Are >> >> >> > >> > you using some sort of a fixed point or fractional type in VHDL, or >> > an >> >> >> > >> > integer type? If you're using integers -- how do you best represent >> > 0.38 >> >> >> > >> > as an integer? >> >> >> > >> >> > >> >> > >> > -- >> >> >> > >> > Tim Wescott >> >> >> > >> > Control system and signal processing consulting >> >> >> > >> > www.wescottdesign.com >> >> >> >> In my VHDL i use std_logic_vector and i want represent fixed point >> >> >> >> example of the division by 4096 >> >> >> >> a11,a12,a21,a22 : in std_logic_vector(15 downto 0); >> >> >> >> b11,b12,b21,b22 : out std_logic_vector(9 downto 0); >> >> >> >> .... >> >> >> >> b11 = "000000" & a11(15 downto 12); -- all positive numbers >> >> b12 = "000000" & a12(15 downto 12); >> >> >> >> So i trunk the decimals, but i don't know... >> >> Thanks very much > > The problem is this: I want manipulate numbers less than zero with fixed > point representation in VHDL, using only std_logic_vector, if is > possible..I wouldn't to use fixed_point packages like in vhdl.org.If your toolset supports VHDL-2008, you could use its built-in fixed point package. Alternatively, if your toolset only supports VHDL-1993, you could try one of the many fixed point packages available for that dielect of VHDL. Or you could roll your own. That works too, but whatever you do, don't overload std_logic_vector to try to give it more meaning than just a bunch of bits. Create your own type, with its own operations - eventually it will morph into something equivalent to the existing fixed- point support. I'm going to go out on a limb here and say that you probably need to take an introductory course in VHDL. BTW, there's a comp.lang.vhdl newsgroup that still has a small amount of traffic. Regards, Allan
Reply by ●November 4, 20132013-11-04
On Sun, 3 Nov 2013 12:14:44 -0800 (PST) Ste_ee <stefano.cap91@gmail.com> wrote:> > The problem is this: I want manipulate numbers less than zero with fixed point representation in VHDL, using only std_logic_vector, if is possible..I wouldn't to use fixed_point packages like in vhdl.org.Please, for the love of all that's holy, don't do that. VHDL is a strongly typed language. Don't abuse it with jerry-rigged pseudo-types; make the right types. If you want a language that you can do whatever you want with so long as you leave a $20 on the nightstand after, write Verilog. As a bare minimum you should be using signed and unsigned from the numeric_std package, rather than std_logic_vector, which I can only assume you're doing math on by bringing in std_logic_arith and friends, which have been poor form since 1993. Before VHDL-2008, that's how I've always done it. On top of that, I write my own subtypes to keep everything clear and rigidly defined in the code. -- Data is S2.16 -- Filter coefficients are S1.17 -- Data * coefficient is S3.33 -- Accumulator needs no overflow bits by design. subtype t_data is signed(17 downto 0); subtype t_coef is signed(17 downto 0); subtype t_product is signed(35 downto 0); subtype t_accum is signed(35 downto 0); As Allan mentioned hwoever, now VHDL-2008 brings in the fixed_pkg as a standard part of the language. A lot of people substantially more knowledgeable than you spent a lot of time writing that (in pure VHDL, by the way) and making it work. You ignore it at your peril. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.
