Fixed Point Analysis and VHDL

Il giorno luned� 4 novembre 2013 18:42:56 UTC+1, Rob Gaddi ha scritto:
> On Sun, 3 Nov 2013 12:14:44 -0800 (PST)
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> Ste_ee <stefano.cap91@gmail.com> wrote:
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> > 
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> > The problem is this: I want manipulate numbers less than zero with fixed point representation in VHDL, using only std_logic_vector, if is possible..I wouldn't to use fixed_point packages like in vhdl.org.
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> Please, for the love of all that's holy, don't do that.  VHDL is a
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> strongly typed language.  Don't abuse it with jerry-rigged
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> pseudo-types; make the right types.  If you want a language that you
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> can do whatever you want with so long as you leave a $20 on the
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> nightstand after, write Verilog.
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> As a bare minimum you should be using signed and unsigned
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> from the numeric_std package, rather than std_logic_vector, which I can
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> only assume you're doing math on by bringing in std_logic_arith and
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> friends, which have been poor form since 1993.
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> Before VHDL-2008, that's how I've always done it.  On top of that, I
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> write my own subtypes to keep everything clear and rigidly defined in
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> the code.
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> -- Data is S2.16
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> -- Filter coefficients are S1.17
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> -- Data * coefficient is S3.33
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> -- Accumulator needs no overflow bits by design.
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> subtype t_data is signed(17 downto 0);
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> subtype t_coef is signed(17 downto 0);
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> subtype t_product is signed(35 downto 0);
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> subtype t_accum is signed(35 downto 0);
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> As Allan mentioned hwoever, now VHDL-2008 brings in the fixed_pkg as a
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> standard part of the language.  A lot of people substantially more
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> knowledgeable than you spent a lot of time writing that (in pure VHDL,
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> by the way) and making it work.  You ignore it at your peril.
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> 
> 
> -- 
> 
> Rob Gaddi, Highland Technology -- www.highlandtechnology.com
> 
> Email address domain is currently out of order.  See above to fix.

All you have been gentiles and thanks very much. I know how 2'complement and vhdl work  but i was only confused about the fixed point representation. Now is all clearly.