Forums

McBSP Interfacing

Started by Barry July 22, 2003
Hi again everyone,

I'm currently writing a driver to interface between the McBsps on my
c6711DSK and the AIC23EVM Codec. Currently I am at the stage where I
can do all the Control (via mcbsp1) and I can also read from the ADCs
on the Codec via McBSP0. My problem though is that I cant write to the
DACs, despite the fact that the the timing diagram for reading and
writing to the codec via McBsp0 is the same.

Control is via McBSP1, and McBSP1 acts as master. Data transfer is via
McBSP0 and this time the Codec acts as master and supplies the Clk and
frame sync for transer of data to the dacs, and from the adc.

I initialize my McBSPs as follws - Note: I initalize SPCR further in
my code.

// CONTROL
MCBSP_Config DSS_mcbspCfg1 = {
    0x02301000,        /*  Serial Port Control Reg. (SPCR)   */
    0x00000040,        /*  Receiver Control Reg. (RCR)   */
    0x00000040,        /*  Transmitter Control Reg. (XCR)   */
    0x20030F03,        /*  Sample-Rate Generator Reg. (SRGR)   */
    0x00000000,        /*  Multichannel Control Reg. (MCR)   */
    0x00000000,        /*  Receiver Channel Enable(RCER)   */
    0x00000000,        /*  Transmitter Channel Enable(XCER)   */
    0x00000A0F         /*  Pin Control Reg. (PCR)   */
};

// DATA TRANSFER
MCBSP_Config DSS_mcbspCfg0 = {
    0x02000000,        /*  Serial Port Control Reg. (SPCR)   */
    0x000100A0,        /*  Receiver Control Reg. (RCR)   */
    0x000000A0,        /*  Transmitter Control Reg. (XCR)   */
    0x30000000,        /*  Sample-Rate Generator Reg. (SRGR)   */
    0x00000000,        /*  Multichannel Control Reg. (MCR)   */
    0x00000000,        /*  Receiver Channel Enable(RCER)   */
    0x00000000,        /*  Transmitter Channel Enable(XCER)   */
    0x0000000E         /*  Pin Control Reg. (PCR)   */
}; 

My Code simply involves polling until the mcbsps are ready to transmit
or recieve audio data. The data I'm recieving is exactly right - I'm
getting the correct number of samples per period for the sin wave
inputing to the Codec.

I'm interested in knowing what McBSP values I should play around with.
I'm not getting any sound what so ever from the headphones when I
attempt to write to the DACS. I have Sidetone (Bypass - Mic to
headphones) enabled, so I can hear sounds if I connect a microphone to
the Mic input.

I've tried reading the Din and Dout values as they are transmitted to
and from the Codec, but they are too fast for my scope to pickup
correctly.

Hope you can help. DSS_init is called from main. Regards, Barry.

Void DSS_init(Void)
{
    Uns t1;
	Uns t2;
	Uns src;
	
	Int i;
	
	Float f1;
	Float f2;
	
	Float div = (float)(0x7fff);
    
   // Enable Transmit and Recieve
   ///////////////////////////////////////////////////////////////
    
    MCBSP_RSETH(DSS_hMcbsp1, SPCR, 0x02F11001);
   
    MCBSP_RSETH(DSS_hMcbsp0, SPCR, 0x02010001);
     
    //////////////////////////////////////////////////////////////

	initRegs();
	
	// poll forever	
	for(;;)	
	for (i=0;i<100000;i++) 
	{	
	
	// sin for output, both left and right channels
    	f1 = f2 = 0.1*cos( ( 2.0 * 3.14 * 300.0 ) * i/44100.0  );
    			
	t1 =  f1 * div;		
	t1 &= 0xffff;
	
        t2 = f2 * div;
	t2 &= 0xffff;
				
	t2 <<= 16;
	t1 = t1 | t2;
		
	// write to DACs
	spWrite(DSS_hMcbsp0, t1);
    	
    	// read from ADCs
    	src = spRead(DSS_hMcbsp0);
    
// convert input data to right and left values in floating point form
	t1 = src &0xffff;
	t2 = (src>>16) & 0xffff;
	
	if(t1 & 0x8000)
	  t1 |= 0xFFFF0000; 
	
	if(t2 & 0x8000)
	  t2 |= 0xFFFF0000; 

	f1 = (((Float)((Int)(t1)))/div);		
	f2 = (((Float)((Int)(t2)))/div);
			
	LOG_printf(&trace,"0");
	LOG_printf(&trace,"%lf",f1);
  }
}

// Read McBsp 
Uns spRead(MCBSP_Handle hMcBsp)
{
// Poll until new value ready to read
	while ((MCBSP_RGETH(DSS_hMcbsp0, SPCR) & 0x2) == 0);
 	return MCBSP_read(hMcBsp);
}

// Write from McBsp to AIC23
Void spWrite(MCBSP_Handle hMcBsp, Uns data)
{
// Poll until ready to transmit
	  while ((MCBSP_RGETH(hMcBsp, SPCR) & 0x20000) == 0);
      MCBSP_write(hMcBsp,data);
}


// Write to a Control Reg on AIC23 
Void aic23_write_reg(Uns uiAddress, Uns uiData)
{
     spWrite(DSS_hMcbsp1, ((uiAddress << 9) | uiData) );
}

//Init AIC23 - CONTROL
static Void initRegs()
{
  
  aic23_write_reg(0x0F, 0x01);        // reset 

  aic23_write_reg(0x0F, 0x00);
  
  aic23_write_reg(0x06, 0x00);        /* power up */
  aic23_write_reg(0x04, 0xf4);        /* aapc */

  aic23_write_reg(0x07, 0x53);        /* daif */

  aic23_write_reg(0x08, (0x8<<2));    /* src */	
  aic23_write_reg(0x09, 0x01);        /* dia */	
}
On 22 Jul 2003 17:53:48 -0700, bg_ie@yahoo.com (Barry) wrote:

>// Poll until new value ready to read > while ((MCBSP_RGETH(DSS_hMcbsp0, SPCR) & 0x2) == 0); > return MCBSP_read(hMcBsp); >} > >// Write from McBsp to AIC23 >Void spWrite(MCBSP_Handle hMcBsp, Uns data) >{ >// Poll until ready to transmit > while ((MCBSP_RGETH(hMcBsp, SPCR) & 0x20000) == 0); > MCBSP_write(hMcBsp,data);
Still don't know why you're not using MCBSP_xrdy and MCBSP_rrdy here! Best Regards John McCabe To reply by email replace 'nospam' with 'assen'
> > while ((MCBSP_RGETH(hMcBsp, SPCR) & 0x20000) == 0); > > MCBSP_write(hMcBsp,data); > > Still don't know why you're not using MCBSP_xrdy and MCBSP_rrdy here!
I want to check all the bits in SPCR. I'm thinking in terms of SPCR - thats all. Both do the same thing anyway. I'm interested in knowing the value of SPCR as I do my polling. What is the bast way of doing this? I've been simply using LOG_printf, but I notice that my code behaves differently when I add more of these statements. Stepping through the code isn't an option, as far as I know, as this is a real time situation. Also I must point out that the Codec is the master of McBSP0. Anyway, with LOG_printf statements in my spWrite() function, I now have this - Void spWrite(MCBSP_Handle hMcBsp, Uns data) { Uns t; // Poll until ready to transmit while (( (t=MCBSP_RGETH(hMcBsp, SPCR)) & 0x20000) == 0) { LOG_printf(&trace,"POLL"); LOG_printf(&trace,"%0x",t); } MCBSP_write(hMcBsp,data); LOG_printf(&trace,"AFTER_POLL"); LOG_printf(&trace,"%0x",t); LOG_printf(&trace,"%0x",MCBSP_RGETH(hMcBsp, SPCR)); } My spRead function takes on a similar format. Surely I can do better than this, any suggestions?? Anyway, when I use this function this is what I get when I do my first audio write to the codec (McBSP0) - X AFTER 2030001 2010001 This translates as meaning that before I call MCBSP_write, XRDY is set, and after its cleared. This is what I would expect. Next I read audio from the codec for the first time, by calling spRead() once, and I get - R POLL 2010001 R POLL 2010001 R POLL 2090009 R POLL 2090009 R POLL 2090009 R POLL 2090009 R POLL 2090009 R POLL 2090009 R POLL 2090009 R POLL 2090009 R POLL 2090009 R POLL 2090009 R POLL 2090009 R POLL 2090009 R POLL 2090009 R POLL 2090009 R AFTE 20f000b 20f0009 The 9s above (0x2090009) indicate that XSYNCERR and RSYNCERR have been set - this happens just after polling commences. Then all together the RRDY, XRDY and XEMPTY bits are all set in SPCR; are set (20f000b above) - Why? Then I read and RRDY is cleared. I then write audio again and I get - X AFTER 20f0009 20d0009 As I continue writing and reading the SYNCERR flags remain set. I then changed my code by commenting out the log_printfs in the spRead function (keeping them in in my spWrite function) I get this the first time I call spWrite(McBSP0) (same value as before)- X AFT 2030001 2010001 but this is what i get the second time I call spWrite - X AFT 2070001 (before write) 2050001 (after write) 0x02050001 in SPCR means that XEMPTY is set. I was under the impression that XEMPTY was cleared when something was writen to the McBSP. Whats going on here? I'm still at the same possition as yesterday, I can read data from the ADCs using spRead, but spWrite does not seem to be working correctly - I'm not even hearing noise from the DACs when I write to them, and I'm positive I have them enabled. As you can see above, spRead goes into a polling state, but spWrite doesn't show the same behaviour. I get the feeling that XEMPTY being set is possibly the root of my problem. When XEMPTY is set, XSR outputs the same value from DXR as last time. Does this mean that the Codec is requesting values quicker than spWrite can supply them? Obviously not... I have tried my code without any log_printfs btw. ;) Thanks as usual for your help, Barry Griffin.
On 22 Jul 2003 17:53:48 -0700, bg_ie@yahoo.com (Barry) wrote:

Just adding some detail for my own benefit...

>Control is via McBSP1, and McBSP1 acts as master. Data transfer is via >McBSP0 and this time the Codec acts as master and supplies the Clk and >frame sync for transer of data to the dacs, and from the adc.
That means data must be ready to be transmitted before the codec wants it.
>// CONTROL >MCBSP_Config DSS_mcbspCfg1 = { > 0x02301000, /* Serial Port Control Reg. (SPCR) */
Bit(s) Field Value Tp ====== ===== ===== == 31..24 Reserved 0x02 R (!) 23 Frame Sync Generator Reset 0x00 RW (Reset) 22 Sample Rate Generator Reset 0x01 RW (Out of Reset) 21..20 Transmit Interrupt Mode 0x11 RW (XINT gen by XSYNCERR) 19 Transmit Sync Error 0x00 RW 18 Transmit SR Empty 0x00 R 17 Transmitter Ready 0x00 R 16 Transmitter Reset 0x00 RW (Disabled) 15 Digital Loopback 0x00 RW (Disabled) 14..13 Receiver Justification 0x00 RW (R Justify and Zero-Fill) 12..11 Clock Stop Mode 0x10 RW (Clockstop No Delay) 10..8 Reserved 0x00 R 7 DX Enabler 0x00 RW (Off) 6 Reserved 0x00 R 5..4 Receiver Interrupt Mode 0x00 RW (RINT Driven by RRDY) 3 Receiver Sync Error 0x00 RW (No frame sync error) 2 Receiver Full 0x00 R 1 Receiver Ready 0x00 R 0 Receiver Reset 0x00 RW (Disabled)
> 0x00000040, /* Receiver Control Reg. (RCR) */ > 0x00000040, /* Transmitter Control Reg. (XCR) */ > 0x20030F03, /* Sample-Rate Generator Reg. (SRGR) */ > 0x00000000, /* Multichannel Control Reg. (MCR) */ > 0x00000000, /* Receiver Channel Enable(RCER) */ > 0x00000000, /* Transmitter Channel Enable(XCER) */ > 0x00000A0F /* Pin Control Reg. (PCR) */ >}; > >// DATA TRANSFER >MCBSP_Config DSS_mcbspCfg0 = { > 0x02000000, /* Serial Port Control Reg. (SPCR) */
Bit(s) Field Value Tp ====== ===== ===== == 31..24 Reserved 0x02 R (!) 23 Frame Sync Generator Reset 0x00 RW (Reset) 22 Sample Rate Generator Reset 0x00 RW (Reset) 21..20 Transmit Interrupt Mode 0x00 RW (XINT driven by XRDY) 19 Transmit Sync Error 0x00 RW 18 Transmit SR Empty 0x00 R 17 Transmitter Ready 0x00 R 16 Transmitter Reset 0x00 RW (Disabled) 15 Digital Loopback 0x00 RW (Disabled) 14..13 Receiver Justification 0x00 RW (R Justify and Zero-Fill) 12..11 Clock Stop Mode 0x00 RW (Clockstop Disabled) 10..8 Reserved 0x00 R 7 DX Enabler 0x00 RW (Off) 6 Reserved 0x00 R 5..4 Receiver Interrupt Mode 0x00 RW (RINT Driven by RRDY) 3 Receiver Sync Error 0x00 RW (No frame sync error) 2 Receiver Full 0x00 R 1 Receiver Ready 0x00 R 0 Receiver Reset 0x00 RW (Disabled)
> 0x000100A0, /* Receiver Control Reg. (RCR) */ > 0x000000A0, /* Transmitter Control Reg. (XCR) */ > 0x30000000, /* Sample-Rate Generator Reg. (SRGR) */ > 0x00000000, /* Multichannel Control Reg. (MCR) */ > 0x00000000, /* Receiver Channel Enable(RCER) */ > 0x00000000, /* Transmitter Channel Enable(XCER) */ > 0x0000000E /* Pin Control Reg. (PCR) */
Now:
> MCBSP_RSETH(DSS_hMcbsp1, SPCR, 0x02F11001);
Bit(s) Field Value Tp ====== ===== ===== == 31..24 Reserved 0x02 R (!) 23 Frame Sync Generator Reset 0x01 RW (Out of Reset) 22 Sample Rate Generator Reset 0x01 RW (Out of Reset) 21..20 Transmit Interrupt Mode 0x11 RW (XINT gen by XSYNCERR) 19 Transmit Sync Error 0x00 RW 18 Transmit SR Empty 0x00 R 17 Transmitter Ready 0x00 R 16 Transmitter Reset 0x01 RW (Enabled) 15 Digital Loopback 0x00 RW (Disabled) 14..13 Receiver Justification 0x00 RW (R Justify and Zero-Fill) 12..11 Clock Stop Mode 0x10 RW (Clockstop No Delay) 10..8 Reserved 0x00 R 7 DX Enabler 0x00 RW (Off) 6 Reserved 0x00 R 5..4 Receiver Interrupt Mode 0x00 RW (RINT Driven by RRDY) 3 Receiver Sync Error 0x00 RW (No frame sync error) 2 Receiver Full 0x00 R 1 Receiver Ready 0x00 R 0 Receiver Reset 0x01 RW (Enabled) So same effect as: MCBSP_enableSrgr(DSS_hMcbsp1); MCBSP_enableRcv (DSS_hMcbsp1); MCBSP_enableXmt (DSS_hMcbsp1); Next:
> MCBSP_RSETH(DSS_hMcbsp0, SPCR, 0x02010001);
Bit(s) Field Value Tp ====== ===== ===== == 31..24 Reserved 0x02 R (!) 23 Frame Sync Generator Reset 0x00 RW (Reset) 22 Sample Rate Generator Reset 0x00 RW (Reset) 21..20 Transmit Interrupt Mode 0x00 RW (XINT driven by XRDY) 19 Transmit Sync Error 0x00 RW 18 Transmit SR Empty 0x00 R 17 Transmitter Ready 0x00 R 16 Transmitter Reset 0x01 RW (Enabled) 15 Digital Loopback 0x00 RW (Disabled) 14..13 Receiver Justification 0x00 RW (R Justify and Zero-Fill) 12..11 Clock Stop Mode 0x00 RW (Clockstop Disabled) 10..8 Reserved 0x00 R 7 DX Enabler 0x00 RW (Off) 6 Reserved 0x00 R 5..4 Receiver Interrupt Mode 0x00 RW (RINT Driven by RRDY) 3 Receiver Sync Error 0x00 RW (No frame sync error) 2 Receiver Full 0x00 R 1 Receiver Ready 0x00 R 0 Receiver Reset 0x01 RW (Enabled) So same effect as: MCBSP_enableRcv (DSS_hMcbsp0); MCBSP_enableXmt (DSS_hMcbsp0); *** Sample Rate Generator not enabled. ***
>// Read McBsp >Uns spRead(MCBSP_Handle hMcBsp) >{ >// Poll until new value ready to read > while ((MCBSP_RGETH(DSS_hMcbsp0, SPCR) & 0x2) == 0);
Checking bit 1 of McBSP0 SPCR => Receiver Ready. Probably won't work because the sample rate generator for McBSP0 is not enabled.
>// Write from McBsp to AIC23 >Void spWrite(MCBSP_Handle hMcBsp, Uns data) >{ >// Poll until ready to transmit > while ((MCBSP_RGETH(hMcBsp, SPCR) & 0x20000) == 0);
Checking bit 17 of McBSP1 SPCR => Transmitter Ready So briefly.... 1) Why are you setting the reserved field at bits 31..24 of the SPCR to 0x02? 2) You need to enable the sample rate generator even if your McBSP is an SPI slave. Note also that, as an SPI slave, you must configure your SRGR such that CLKGDV allows for as high a sample rate as possible. In fact, the sample rate must be at least 8 times the bit rate. (See section 11.7.2 of the TMS320C6000 Peripherals Reference Guide version C - SPRU190C) 3) In your McBSP0 RCR you're setting the receiver data delay (bit 16) to 1 bit. When the McBSP is an SPI slave this should be set to zero. Does this help? Best Regards John McCabe To reply by email replace 'nospam' with 'assen'
Barry

Just wanted to check you'd read my other message on 24/07/2003 15:16?

There are a few points at the bottom that you may not have got as far
as but which look like a likely candidate for your McBSP not working!


Best Regards
John McCabe

To reply by email replace 'nospam' with 'assen'
Thanks for your help John, the problem didn't lie with the McBSPs
after all, but with how I was setting up the control on the codec. The
Codec has 11 registers which are set with default values on reset. I
was setting about half of these registers because the remainder with
set with the desired values. As it turns out, if you write to the 5th
register the DAC suddenly starts working - it doesn't matter what you
write to it, and I'm still not setting a number of other registers.
This 5th register is concerned with filtering of the DAC and ADC
outputs and inputs respectfully. The ADC works without writing to this
register and the manual mentions nothing about writing to this reg. if
ou expect the DAC to work.

I was writing to all the registers at one point, put I must have been
doing something else wrong at that point - you live and learn.

Thanks again, 

Barry.


john@nospam.demon.co.uk (John McCabe) wrote in message news:<3f1fe1de.16961889@news.btclick.com>...
> On 22 Jul 2003 17:53:48 -0700, bg_ie@yahoo.com (Barry) wrote: > > Just adding some detail for my own benefit... > > >Control is via McBSP1, and McBSP1 acts as master. Data transfer is via > >McBSP0 and this time the Codec acts as master and supplies the Clk and > >frame sync for transer of data to the dacs, and from the adc. > > That means data must be ready to be transmitted before the codec wants > it. > > >// CONTROL > >MCBSP_Config DSS_mcbspCfg1 = { > > 0x02301000, /* Serial Port Control Reg. (SPCR) */ > > Bit(s) Field Value Tp > ====== ===== ===== == > 31..24 Reserved 0x02 R (!) > 23 Frame Sync Generator Reset 0x00 RW (Reset) > 22 Sample Rate Generator Reset 0x01 RW (Out of Reset) > 21..20 Transmit Interrupt Mode 0x11 RW (XINT gen by XSYNCERR) > 19 Transmit Sync Error 0x00 RW > 18 Transmit SR Empty 0x00 R > 17 Transmitter Ready 0x00 R > 16 Transmitter Reset 0x00 RW (Disabled) > 15 Digital Loopback 0x00 RW (Disabled) > 14..13 Receiver Justification 0x00 RW (R Justify and Zero-Fill) > 12..11 Clock Stop Mode 0x10 RW (Clockstop No Delay) > 10..8 Reserved 0x00 R > 7 DX Enabler 0x00 RW (Off) > 6 Reserved 0x00 R > 5..4 Receiver Interrupt Mode 0x00 RW (RINT Driven by RRDY) > 3 Receiver Sync Error 0x00 RW (No frame sync error) > 2 Receiver Full 0x00 R > 1 Receiver Ready 0x00 R > 0 Receiver Reset 0x00 RW (Disabled) > > > 0x00000040, /* Receiver Control Reg. (RCR) */ > > 0x00000040, /* Transmitter Control Reg. (XCR) */ > > 0x20030F03, /* Sample-Rate Generator Reg. (SRGR) */ > > 0x00000000, /* Multichannel Control Reg. (MCR) */ > > 0x00000000, /* Receiver Channel Enable(RCER) */ > > 0x00000000, /* Transmitter Channel Enable(XCER) */ > > 0x00000A0F /* Pin Control Reg. (PCR) */ > >}; > > > >// DATA TRANSFER > >MCBSP_Config DSS_mcbspCfg0 = { > > 0x02000000, /* Serial Port Control Reg. (SPCR) */ > > Bit(s) Field Value Tp > ====== ===== ===== == > 31..24 Reserved 0x02 R (!) > 23 Frame Sync Generator Reset 0x00 RW (Reset) > 22 Sample Rate Generator Reset 0x00 RW (Reset) > 21..20 Transmit Interrupt Mode 0x00 RW (XINT driven by XRDY) > 19 Transmit Sync Error 0x00 RW > 18 Transmit SR Empty 0x00 R > 17 Transmitter Ready 0x00 R > 16 Transmitter Reset 0x00 RW (Disabled) > 15 Digital Loopback 0x00 RW (Disabled) > 14..13 Receiver Justification 0x00 RW (R Justify and Zero-Fill) > 12..11 Clock Stop Mode 0x00 RW (Clockstop Disabled) > 10..8 Reserved 0x00 R > 7 DX Enabler 0x00 RW (Off) > 6 Reserved 0x00 R > 5..4 Receiver Interrupt Mode 0x00 RW (RINT Driven by RRDY) > 3 Receiver Sync Error 0x00 RW (No frame sync error) > 2 Receiver Full 0x00 R > 1 Receiver Ready 0x00 R > 0 Receiver Reset 0x00 RW (Disabled) > > > 0x000100A0, /* Receiver Control Reg. (RCR) */ > > 0x000000A0, /* Transmitter Control Reg. (XCR) */ > > 0x30000000, /* Sample-Rate Generator Reg. (SRGR) */ > > 0x00000000, /* Multichannel Control Reg. (MCR) */ > > 0x00000000, /* Receiver Channel Enable(RCER) */ > > 0x00000000, /* Transmitter Channel Enable(XCER) */ > > 0x0000000E /* Pin Control Reg. (PCR) */ > > Now: > > > MCBSP_RSETH(DSS_hMcbsp1, SPCR, 0x02F11001); > > Bit(s) Field Value Tp > ====== ===== ===== == > 31..24 Reserved 0x02 R (!) > 23 Frame Sync Generator Reset 0x01 RW (Out of Reset) > 22 Sample Rate Generator Reset 0x01 RW (Out of Reset) > 21..20 Transmit Interrupt Mode 0x11 RW (XINT gen by XSYNCERR) > 19 Transmit Sync Error 0x00 RW > 18 Transmit SR Empty 0x00 R > 17 Transmitter Ready 0x00 R > 16 Transmitter Reset 0x01 RW (Enabled) > 15 Digital Loopback 0x00 RW (Disabled) > 14..13 Receiver Justification 0x00 RW (R Justify and Zero-Fill) > 12..11 Clock Stop Mode 0x10 RW (Clockstop No Delay) > 10..8 Reserved 0x00 R > 7 DX Enabler 0x00 RW (Off) > 6 Reserved 0x00 R > 5..4 Receiver Interrupt Mode 0x00 RW (RINT Driven by RRDY) > 3 Receiver Sync Error 0x00 RW (No frame sync error) > 2 Receiver Full 0x00 R > 1 Receiver Ready 0x00 R > 0 Receiver Reset 0x01 RW (Enabled) > > So same effect as: > > MCBSP_enableSrgr(DSS_hMcbsp1); > MCBSP_enableRcv (DSS_hMcbsp1); > MCBSP_enableXmt (DSS_hMcbsp1); > > Next: > > > MCBSP_RSETH(DSS_hMcbsp0, SPCR, 0x02010001); > > Bit(s) Field Value Tp > ====== ===== ===== == > 31..24 Reserved 0x02 R (!) > 23 Frame Sync Generator Reset 0x00 RW (Reset) > 22 Sample Rate Generator Reset 0x00 RW (Reset) > 21..20 Transmit Interrupt Mode 0x00 RW (XINT driven by XRDY) > 19 Transmit Sync Error 0x00 RW > 18 Transmit SR Empty 0x00 R > 17 Transmitter Ready 0x00 R > 16 Transmitter Reset 0x01 RW (Enabled) > 15 Digital Loopback 0x00 RW (Disabled) > 14..13 Receiver Justification 0x00 RW (R Justify and Zero-Fill) > 12..11 Clock Stop Mode 0x00 RW (Clockstop Disabled) > 10..8 Reserved 0x00 R > 7 DX Enabler 0x00 RW (Off) > 6 Reserved 0x00 R > 5..4 Receiver Interrupt Mode 0x00 RW (RINT Driven by RRDY) > 3 Receiver Sync Error 0x00 RW (No frame sync error) > 2 Receiver Full 0x00 R > 1 Receiver Ready 0x00 R > 0 Receiver Reset 0x01 RW (Enabled) > > So same effect as: > > MCBSP_enableRcv (DSS_hMcbsp0); > MCBSP_enableXmt (DSS_hMcbsp0); > > *** Sample Rate Generator not enabled. *** > > >// Read McBsp > >Uns spRead(MCBSP_Handle hMcBsp) > >{ > >// Poll until new value ready to read > > while ((MCBSP_RGETH(DSS_hMcbsp0, SPCR) & 0x2) == 0); > > Checking bit 1 of McBSP0 SPCR => Receiver Ready. > > Probably won't work because the sample rate generator for McBSP0 is > not enabled. > > >// Write from McBsp to AIC23 > >Void spWrite(MCBSP_Handle hMcBsp, Uns data) > >{ > >// Poll until ready to transmit > > while ((MCBSP_RGETH(hMcBsp, SPCR) & 0x20000) == 0); > > Checking bit 17 of McBSP1 SPCR => Transmitter Ready > > > So briefly.... > > 1) Why are you setting the reserved field at bits 31..24 of the SPCR > to 0x02? > > 2) You need to enable the sample rate generator even if your McBSP is > an SPI slave. Note also that, as an SPI slave, you must configure your > SRGR such that CLKGDV allows for as high a sample rate as possible. In > fact, the sample rate must be at least 8 times the bit rate. (See > section 11.7.2 of the TMS320C6000 Peripherals Reference Guide version > C - SPRU190C) > > 3) In your McBSP0 RCR you're setting the receiver data delay (bit 16) > to 1 bit. When the McBSP is an SPI slave this should be set to zero. > > Does this help? > > > Best Regards > John McCabe > > To reply by email replace 'nospam' with 'assen'