Hi all,
I'm writing a driver to allow me to communicate from my C6711 to the
TLV320AIC23EVM Audio Codec. This communication involves writing the
control registers via mcbsp1 and streaming the audio data via mcbsp0.
I'm currently trying to write to the control registers on the codec
but I'm not sure if I'm doing it right. I have jumped JP1 on my DSP
board to connect mcbsp0 to the AIC23 daughter board. My audiocfg_c.c
file looks something like this ( I've excluded McBsp0 and its EDMA
setup)
#include "audiocfg.h"
MCBSP_Config DSS_mcbspCfg1 = {
0x02001000, // SPCR : free running mode
0x00000040, // RCR : 16 bit receive data length
0x00000040, // XCR : 16 bit transmit data length
0x20041080,
0x00000000, // MCR : single channel
0x00000000, // RCER : disable read channels
0x00000000, // XCER : disable write channels
0x00000A0F, // PCR : FSX, FSR active low, internal FS/CLK source
};
MCBSP_Handle DSS_hMcbsp1;
void CSL_cfgInit()
{
DSS_hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
MCBSP_config(DSS_hMcbsp1, &DSS_mcbspCfg1);
}
In the main function I then try the following -
main()
{
MCBSP_enableXmt(DSS_hMcbsp1);
DSS_spWrite(0x97); // Write to the first register of the Codec
DSS_spWrite(0x297); // Write to the second register of the Codec
DSS_spWrite(0x4F9); // Write to the third register of the Codec
}
Void DSS_spWrite(Uns data)
{
while ((MCBSP_RGETH(DSS_hMcbsp1, SPCR) & 0x20000) == 0)
{
LOG_printf(&trace,"*");
}
MCBSP_write(DSS_hMcbsp0,data);
}
I'm never entering the while loop - "*" is never printed - does that
sound correct?
The timing for the SPI Control Interface between McBsp1 and the Codec
is as follows -
______ _____
__ \ /
CS \ /
\ /
\_____________________________ // _________/
____ _____ __ // __ _____
\ / \ / \ /
\ / \ / \ /
SCLK \ / \ / \ /
\_____/ \______/ \_____/
____ _______________ _________ // ____ ____________
\ / \ / \ /
\/ \/ \/
DIN /\ /\ /\
_____/ \_______________/ \_________ // ____/ \____________
__
CS = FSX1
SCLK = CLKX1
DIN = DX1
I've tried setting SCLK for both slave and master (CLKXM) but I'm only
getting a 2 Volt DC voltage at its test point on the daughter board,
the AC signal is in the 0.1 Volt range and is very noisy. I'm not
actually seeing any AC signals at the CS, SCLK, and DIN test points.
Before I inserted the C6711 Jumper, I could see data signals entering
and leaving the 353 Codec on the c6711 when I ran audio.pjt, an
example project for the C6711 codec. I'm using the HITACHI V-252 20MHz
Oscilliscope.
What might I be doing wrong? What McBSP register values might I try
instead? Any signals on the C6711 that might be worth checking out
with my scope? Where on the C6711 are the McBSPs? I've inserted a
jumper on the c6711, should I be perhaps doing something else also in
order to enable the daughter board interface? Any other suggestions
that might be helpful?
I have the AIC23EVM jumpers in their default positions.
Data sheets for the AIC23 and AIC23EVM -
http://www.tij.co.jp/jsc/docs/msp/pcm/pdf/m_dac/tlv320aic23.pdf
http://www.lami.pucpr.br/~afonso/Graduacao/Outros/Audio/tlv320aic23-manual.pdf
Thanks for your help,
Barry Griffin.
McBSP Interfacing Question
Started by ●July 18, 2003
Reply by ●July 18, 20032003-07-18
bg_ie@yahoo.com (Barry) wrote: I'm not sure I can help, but a couple of questions might help you on your way...>but I'm not sure if I'm doing it right. I have jumped JP1 on my DSP >board to connect mcbsp0 to the AIC23 daughter board.Is that a C6711 DSK?>void CSL_cfgInit() >{ > DSS_hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET); > MCBSP_config(DSS_hMcbsp1, &DSS_mcbspCfg1); >} > >In the main function I then try the following - > >main() >{ > MCBSP_enableXmt(DSS_hMcbsp1); > DSS_spWrite(0x97); // Write to the first register of the Codec > DSS_spWrite(0x297); // Write to the second register of the Codec > DSS_spWrite(0x4F9); // Write to the third register of the Codec >}Where do you enable your Sample Rate Generator (SRGR)? What is the SRGR configuration? As this appears to be an SPI interface, should you also enable receive on that McBSP?> while ((MCBSP_RGETH(DSS_hMcbsp1, SPCR) & 0x20000) == 0)What does MCBSP_RGETH do? What are you trying to achieve at this point (this may be obvious but I don't have the docs to hand to work this out and I'm not familiar with MCBSP_RGETH). Saying that though, it sound like something to do with receiving, but you don't appear to have enabled the receive part of the McBSP.>I'm never entering the while loop - "*" is never printed - does that >sound correct?Not sure...>What might I be doing wrong? What McBSP register values might I try >instead? Any signals on the C6711 that might be worth checking out >with my scope? Where on the C6711 are the McBSPs? I've inserted a >jumper on the c6711, should I be perhaps doing something else also in >order to enable the daughter board interface? Any other suggestions >that might be helpful?See comments above. For more information on the C6711 see sprs088g.pdf on the TI website: http://focus.ti.com/lit/ds/sprs088g/sprs088g.pdf Also, if you haven't already got it, the Peripherals Reference Guide is very useful: http://focus.ti.com/lit/ug/spru190d/spru190d.pdf Hope some of this is of use. Best Regards John McCabe <john@assen.demon.co.uk>
Reply by ●July 19, 20032003-07-19
> Is that a C6711 DSK?Yes> Where do you enable your Sample Rate Generator (SRGR)?MCBSP_Config DSS_mcbspCfg1 = { 0x02001000, // SPCR : free running mode 0x00000040, // RCR : 16 bit receive data length 0x00000040, // XCR : 16 bit transmit data length 0x20041080, // SRGR 0x00000000, // MCR : single channel 0x00000000, // RCER : disable read channels 0x00000000, // XCER : disable write channels 0x00000A0F, // PCR : FSX, FSR active low, internal FS/CLK source };> What is the SRGR configuration?SRGR = 0x20041080, which = CLKGDV 0x80 FWID 0x10 FPER 0x004 FSGM 0b CLKSM 1b CLKSP 0b GSYSC 0b> As this appears to be an SPI interface, should you also enable receive > on that McBSP?It is SPI. DR1 is not used by the codec. Control involves setting up registers on the Codec - these registers can not be read.> > > while ((MCBSP_RGETH(DSS_hMcbsp1, SPCR) & 0x20000) == 0) > > What does MCBSP_RGETH do? What are you trying to achieve at this point > (this may be obvious but I don't have the docs to hand to work this > out and I'm not familiar with MCBSP_RGETH). Saying that though, it > sound like something to do with receiving, but you don't appear to > have enabled the receive part of the McBSP. >I am checking if the transmitter (on mcbsp 1) is ready for new data in DXR. Thanks for your help, suggestions still very much appreciated, Regards, Barry Griffin.
Reply by ●July 19, 20032003-07-19
Hi again,
I forgot to mention that its the c6711 DSK that I'm using.
Anyway, I removed the daughterboard and examined the signals belonging
to U24A. This is the LVL_SHFT for McBSP1, and I should be able to see
the clk, frame sync and data signals going in and out of this chip.
Unfortunately, I'm not seeing any AC signals at the pins to or from
this chip - that is, I dont see anything that might look like clock or
data information.
If the daughterboard if disconnected, am I right in saying that I
should be able to see the clkx signal with my ocilloscope if I have
mcbsp1 configured as master, and transmit enabled? I cant examine the
u24 when the daughter board is installed. I've spent all day playing
around with my code and I cant see the expected signals. Nor can I see
them when the daughter board is connected.
All I want to see are some clk signals coming from mcbsp1; just to see
that at this point would be encouraging.
I've also tried using the exact same code only configured for mcbsp0.
I then examined U34 and U35, which are the Muxs associated with
mcbsp0. I'm again not seeing any clk or data like signals except for
the sclk signal concerning the 535 codec (the c6711 onboard codec). I
have installed a jumper at JP1 and this means that this signal is not
inputed to the c6711 processor.
Perhaps the signals are too high frequency for a 20MHz Oscilloscope.
But I guess I should see a blur between its min and max amplitudes.
Anyway here is the code I'm now using. Hopefully someone will notice
what I'm doing wrong...
Maybe someone might be interested in trying this code on their own
dsk, to see what happens. ;)
#include "audiocfg.h"
MCBSP_Config DSS_mcbspCfg1 = {
0x02301000, /* Serial Port Control Reg. (SPCR) */
0x00000040, /* Receiver Control Reg. (RCR) */
0x00000040, /* Transmitter Control Reg. (XCR) */
0x20041004, /* Sample-Rate Generator Reg. (SRGR) */
0x00000000, /* Multichannel Control Reg. (MCR) */
0x00000000, /* Receiver Channel Enable(RCER) */
0x00000000, /* Transmitter Channel Enable(XCER) */
0x0000080F /* Pin Control Reg. (PCR) */
};
MCBSP_Handle DSS_hMcbsp1;
void CSL_cfgInit()
{
DSS_hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
MCBSP_config(DSS_hMcbsp1, &DSS_mcbspCfg1);
}
main
{
MCBSP_RSETH(DSS_hMcbsp1, SPCR, 0x02301000);
MCBSP_RSETH(DSS_hMcbsp1, SPCR, 0x02701000);
// delay (1+CLKGDV) * 2
LOG_printf(&trace,"DELAY");
MCBSP_RSETH(DSS_hMcbsp1, SPCR, 0x02701001);
MCBSP_RSETH(DSS_hMcbsp1, SPCR, 0x02711001);
MCBSP_RSETH(DSS_hMcbsp1, SPCR, 0x02F11001);
aic23_write_reg(0x0F, 0x01); /* reset codec*/
aic23_write_reg(0x0F, 0x00); /* reset codec*/
}
Void aic23_write_reg(Uns uiAddress, Uns uiData)
{
Uns uiRegData;
uiRegData = (uiAddress << 9) | uiData;
CNT_spWrite(uiRegData);
}
Void CNT_spWrite(Uns data)
{
while ((MCBSP_RGETH(DSS_hMcbsp1, SPCR) & 0x20000) == 0)
{
LOG_printf(&trace,"*");
}
MCBSP_write(DSS_hMcbsp0,data);
}
Reply by ●July 19, 20032003-07-19
bg_ie@yahoo.com (Barry) wrote:>> Where do you enable your Sample Rate Generator (SRGR)?>MCBSP_Config DSS_mcbspCfg1 = {> 0x02001000, // SPCR : free running mode > 0x00000040, // RCR : 16 bit receive data length > 0x00000040, // XCR : 16 bit transmit data length > 0x20041080, // SRGR > 0x00000000, // MCR : single channel > 0x00000000, // RCER : disable read channels > 0x00000000, // XCER : disable write channels > 0x00000A0F, // PCR : FSX, FSR active low, internal FS/CLK source >};Oh right. I have it enabled separately after teh configuration. My configuration parameters leave transmit, receive and SRGR inactive then enabled in that order.>> What is the SRGR configuration?>> As this appears to be an SPI interface, should you also enable receive >> on that McBSP? > >It is SPI. DR1 is not used by the codec. Control involves setting up >registers on the Codec - these registers can not be read.Well, yes - but wouldn't do any harm to try enabling the receiver :-)>> >> > while ((MCBSP_RGETH(DSS_hMcbsp1, SPCR) & 0x20000) == 0) >> >> What does MCBSP_RGETH do? What are you trying to achieve at this point >> (this may be obvious but I don't have the docs to hand to work this >> out and I'm not familiar with MCBSP_RGETH). Saying that though, it >> sound like something to do with receiving, but you don't appear to >> have enabled the receive part of the McBSP. >> > >I am checking if the transmitter (on mcbsp 1) is ready for new data in >DXR.Oh yes - I see, RGETH is reads a specific register given a handle. Why not use MCBSP_xrdy?>Thanks for your help, suggestions still very much appreciated,No problem. Sorry they weren't of much use but once I've got more information in front of me (on Monday) I might spot something! Best Regards John McCabe <john@assen.demon.co.uk>
Reply by ●July 20, 20032003-07-20
john@nospam.assen.demon.co.uk.nospam (John McCabe) wrote:>As this appears to be an SPI interface, should you also enable receive >on that McBSP? > >> while ((MCBSP_RGETH(DSS_hMcbsp1, SPCR) & 0x20000) == 0) > >What does MCBSP_RGETH do? What are you trying to achieve at this pointMacros used by BIOS to get the value of SPCR ... which is being and'd with the relevant bit. Robert www.gldsp.com ( modify address for return email ) www.numbersusa.com www.americanpatrol.com
