On 12/19/14 10:06 AM, rickman wrote:> I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS.i still get the concepts of DDS and NCO mixed up. what are the differences? is this a circuit with an analog output? or are you looking at the stream of samples before they get to the D/A converter?> My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too easy > to get such good results. I guess I'm worried that it will be hard to > measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code.okay so you're at the samples before they're output to the D/A. instead of, i presume windowing with a decent window (like a Kaiser, but a Hamming might do in a pinch), using the FFT and looking for how clean the spike is, i would suggest a notch filter tuned to the frequency that you *know* is coming out of the NCO because you know the phase increment. or is this DDS generated differently than an NCO, like using some recursion equation? anyway, whatever comes out of that precisely-tuned, narrowband notch filter is the error signal. if there are spurs or whatever distortion, it will be in that notch filter output.> The implementation will be synthesizable and the > measurement code will not.i dunno what synthesizable code is.> I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point.i wouldn't bother with the FFT unless you want to run it on the notch filter output. if you have an FFT in your toolbag, it sounds like your code is floating point. is that the case? because with "vhdl", that sounds like it might be a fixed-point architecture. -- r b-j rbj@audioimagination.com "Imagination is more important than knowledge."
Spectral Purity Measurement
Started by ●December 19, 2014
Reply by ●December 19, 20142014-12-19
Reply by ●December 19, 20142014-12-19
On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson wrote:> On 12/19/14 10:06 AM, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an >> FFT is the best way to do this. I'm mainly concerned with the "close >> in" spurs that are often generated by a DDS. > > i still get the concepts of DDS and NCO mixed up. what are the > differences? > > is this a circuit with an analog output? or are you looking at the > stream of samples before they get to the D/A converter? > > >> My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too >> easy to get such good results. I guess I'm worried that it will be hard >> to measure such low levels. >> >> Any suggestions? I'll be coding both the implementation and the >> measurement code. > > okay so you're at the samples before they're output to the D/A. instead > of, i presume windowing with a decent window (like a Kaiser, but a > Hamming might do in a pinch), using the FFT and looking for how clean > the spike is, i would suggest a notch filter tuned to the frequency that > you *know* is coming out of the NCO because you know the phase > increment. or is this DDS generated differently than an NCO, like using > some recursion equation? anyway, whatever comes out of that > precisely-tuned, narrowband notch filter is the error signal. if there > are spurs or whatever distortion, it will be in that notch filter > output. > >> The implementation will be synthesizable and the measurement code will >> not. > > i dunno what synthesizable code is.Synthesizable code is code that the tool knows how to make into FPGA firmware. HDL projects generally have both a hardware description component which is synthesizable (or at least one fervently hopes) and a test component which generally is not. The tools will simulate the whole design under the control of the test component.>> I'm thinking a fairly large FFT, 2048 or maybe 4096 bins in floating >> point. > > i wouldn't bother with the FFT unless you want to run it on the notch > filter output. if you have an FFT in your toolbag, it sounds like your > code is floating point. is that the case? because with "vhdl", that > sounds like it might be a fixed-point architecture.The test component can have floating point. For that matter, FPGAs are big enough to support code bloat these days; it's not unheard of to have floating-point math on them, although I think that fixed-point math is still the most common. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●December 20, 20142014-12-20
On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson <rbj@audioimagination.com> wrote:>On 12/19/14 10:06 AM, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an FFT >> is the best way to do this. I'm mainly concerned with the "close in" >> spurs that are often generated by a DDS. > >i still get the concepts of DDS and NCO mixed up. what are the differences?One is spelled DDS and the other is spelled NCO. They're basically the same thing, like 4WD and AWD. The difference is mostly marketing. ;)>is this a circuit with an analog output? or are you looking at the >stream of samples before they get to the D/A converter? > > >> My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too easy >> to get such good results. I guess I'm worried that it will be hard to >> measure such low levels. >> >> Any suggestions? I'll be coding both the implementation and the >> measurement code. > >okay so you're at the samples before they're output to the D/A. instead >of, i presume windowing with a decent window (like a Kaiser, but a >Hamming might do in a pinch), using the FFT and looking for how clean >the spike is, i would suggest a notch filter tuned to the frequency that >you *know* is coming out of the NCO because you know the phase >increment. or is this DDS generated differently than an NCO, like using >some recursion equation? anyway, whatever comes out of that >precisely-tuned, narrowband notch filter is the error signal. if there >are spurs or whatever distortion, it will be in that notch filter output. > >> The implementation will be synthesizable and the >> measurement code will not. > >i dunno what synthesizable code is.Hardware Description Language that can be synthesized to gates or other hardware.>> I'm thinking a fairly large FFT, 2048 or >> maybe 4096 bins in floating point. > >i wouldn't bother with the FFT unless you want to run it on the notch >filter output. if you have an FFT in your toolbag, it sounds like your >code is floating point. is that the case? because with "vhdl", that >sounds like it might be a fixed-point architecture. > > >-- > >r b-j rbj@audioimagination.com > >"Imagination is more important than knowledge." > >Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com
Reply by ●December 20, 20142014-12-20
On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote:> I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too > easy to get such good results. I guess I'm worried that it will be hard > to measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. The implementation will be synthesizable and the > measurement code will not. I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point.1ppm would be 120dBc, surely... (20 bits) I believe you can subtract an ideal signal, then FFT the remainder. You may also want to downconvert to a relatively low frequency so that you can get a decent bin spacing to examine close-in spurs. - Brian
Reply by ●December 20, 20142014-12-20
On Fri, 19 Dec 2014 18:19:24 -0500, robert bristow-johnson <rbj@audioimagination.com> wrote:>On 12/19/14 10:06 AM, rickman wrote: >> I want to analyze the output of a DDS circuit and am wondering if an FFT >> is the best way to do this. I'm mainly concerned with the "close in" >> spurs that are often generated by a DDS. > >i still get the concepts of DDS and NCO mixed up. what are the differences?According to Wikipedia (under "numerically controlled oscillator") the NCO is the digital part, which drives a DAC to make a DDS. Bob Masta DAQARTA v7.60 Data AcQuisition And Real-Time Analysis www.daqarta.com Scope, Spectrum, Spectrogram, Sound Level Meter Frequency Counter, Pitch Track, Pitch-to-MIDI FREE Signal Generator, DaqMusiq generator Science with your sound card!
Reply by ●December 20, 20142014-12-20
On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote:> I want to analyze the output of a DDS circuit and am wondering if an FFT > is the best way to do this. I'm mainly concerned with the "close in" > spurs that are often generated by a DDS. My analysis of the errors > involved in the sine generation is that they will be on the order of 1 > ppm which I believe will be -240 dBc. Is that right? Sounds far too > easy to get such good results. I guess I'm worried that it will be hard > to measure such low levels. > > Any suggestions? I'll be coding both the implementation and the > measurement code. The implementation will be synthesizable and the > measurement code will not. I'm thinking a fairly large FFT, 2048 or > maybe 4096 bins in floating point.BTW, you are looking for spurs at -120dBc, not -240dBc. An FFT is part of the solution, but naively FFTing the DDS output waveform won't give you good results. Consider the difference between a regular Spectrum Analyser and a Phase Noise test set. The Phase Noise test set is really just a sort of spectrum analyser but it is designed for looking at low level phase noise. Keysight (used to be Agilent) claim to have a sensitivity of about -180 dBc/Hz on their top of the line model. That's an awful lot better than any regular SA. (It also claims to work to 110GHz.) The trick is to get rid of the carrier before calculating the spectrum. The FFT only needs to see the noise, rather than the signal + noise. May I suggest you do the following in your HDL simulation: 1. Generate an "ideal" reference waveform. Use floating point (but use it carefully). 2. Mix this ideal waveform with the waveform from your simulated DDS. You can use a real mixer (i.e. a multiplier). The ideal waveform and the DDS output must be close to pi/2 out of phase. The accuracy of this phase shift determines the amount of carrier cancellation. 3. Get rid of the 2F component at the output of the mixer, i.e. low pass filter. 4. FFT the output of the lpf. 5a Spend half an hour scratching your head trying to work out how to interpret the results. 5b. Decide that the maths is beyond human comprehension. At this point, you either refer to some HP system journal from last century, or determine the scale factors empirically by measuring a test signal with a known amount of phase or frequency modulation. Allan
Reply by ●December 20, 20142014-12-20
On Sat, 20 Dec 2014 13:43:55 +0000, Allan Herriman wrote:> On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote: > >> I want to analyze the output of a DDS circuit and am wondering if an >> FFT is the best way to do this. I'm mainly concerned with the "close >> in" spurs that are often generated by a DDS. My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too >> easy to get such good results. I guess I'm worried that it will be >> hard to measure such low levels. >> >> Any suggestions? I'll be coding both the implementation and the >> measurement code. The implementation will be synthesizable and the >> measurement code will not. I'm thinking a fairly large FFT, 2048 or >> maybe 4096 bins in floating point. > > > BTW, you are looking for spurs at -120dBc, not -240dBc. > > > An FFT is part of the solution, but naively FFTing the DDS output > waveform won't give you good results. > > Consider the difference between a regular Spectrum Analyser and a Phase > Noise test set. The Phase Noise test set is really just a sort of > spectrum analyser but it is designed for looking at low level phase > noise. Keysight (used to be Agilent) claim to have a sensitivity of > about -180 dBc/Hz on their top of the line model. That's an awful lot > better than any regular SA. (It also claims to work to 110GHz.) > > The trick is to get rid of the carrier before calculating the spectrum. > The FFT only needs to see the noise, rather than the signal + noise. > > May I suggest you do the following in your HDL simulation: > > 1. Generate an "ideal" reference waveform. Use floating point (but use > it carefully). > > 2. Mix this ideal waveform with the waveform from your simulated DDS. > You can use a real mixer (i.e. a multiplier). The ideal waveform and > the DDS output must be close to pi/2 out of phase. The accuracy of this > phase shift determines the amount of carrier cancellation. > > 3. Get rid of the 2F component at the output of the mixer, i.e. low > pass filter. > > 4. FFT the output of the lpf. > > 5a Spend half an hour scratching your head trying to work out how to > interpret the results. > > 5b. Decide that the maths is beyond human comprehension. At this > point, > you either refer to some HP system journal from last century, or > determine the scale factors empirically by measuring a test signal with > a known amount of phase or frequency modulation. > > Allanoops, forgot to mention that after you get rid of the carrier by mixing down to 0Hz (in step 2) and removing the 2F components (in step 3), you can decimate the signal to reduce the bandwidth. This allows you to avoid the need to calculate monster FFTs if you're only interested in the "close in" spurs. Allan
Reply by ●December 20, 20142014-12-20
In comp.dsp Allan Herriman <allanherriman@hotmail.com> wrote:> On Fri, 19 Dec 2014 10:06:50 -0500, rickman wrote:>> I want to analyze the output of a DDS circuit and am wondering if an FFT >> is the best way to do this. I'm mainly concerned with the "close in" >> spurs that are often generated by a DDS. My analysis of the errors >> involved in the sine generation is that they will be on the order of 1 >> ppm which I believe will be -240 dBc. Is that right? Sounds far too >> easy to get such good results. I guess I'm worried that it will be hard >> to measure such low levels.(snip)> BTW, you are looking for spurs at -120dBc, not -240dBc.> An FFT is part of the solution, but naively FFTing the DDS output > waveform won't give you good results.> Consider the difference between a regular Spectrum Analyser and a Phase > Noise test set. The Phase Noise test set is really just a sort of > spectrum analyser but it is designed for looking at low level phase > noise. Keysight (used to be Agilent) claim to have a sensitivity of > about -180 dBc/Hz on their top of the line model. That's an awful lot > better than any regular SA. (It also claims to work to 110GHz.)> The trick is to get rid of the carrier before calculating the spectrum. > The FFT only needs to see the noise, rather than the signal + noise.> May I suggest you do the following in your HDL simulation:> 1. Generate an "ideal" reference waveform. Use floating point(but use it carefully). My choice would be fixed point. With fixed point, you know exactly how the rounding is done, and it is done independent of the size of the values at any point in the computation. You could, for example, use 64 bit fixed point instead of 64 bit floating point.> 2. Mix this ideal waveform with the waveform from your simulated DDS. > You can use a real mixer (i.e. a multiplier). The ideal waveform and the > DDS output must be close to pi/2 out of phase. The accuracy of this > phase shift determines the amount of carrier cancellation.Pretty much you are computing, and then subtracting, one frequency (Fourier) component from the signal. You need enough bits (accuracy) to not have rounding contribute to the result (noise).> 3. Get rid of the 2F component at the output of the mixer, > i.e. low pass filter.> 4. FFT the output of the lpf.For fixed point FFT, the values can increase one bit at each stage of the FFT. On average they will increase by sqrt(2) (RMS), but if the orginal carrier is still there, you likely get an increase by a factor of 2 in some bin. If you have enough bits, original signal resolution plus log2(FFT length) seems to me you could just run it through the FFT. Well, that might work best if the carrier was in a single bin.> 5a Spend half an hour scratching your head trying to work out how to > interpret the results.> 5b. Decide that the maths is beyond human comprehension. At this point, > you either refer to some HP system journal from last century, or > determine the scale factors empirically by measuring a test signal with a > known amount of phase or frequency modulation.-- glen
Reply by ●December 21, 20142014-12-21
On Sat, 20 Dec 2014 19:43:33 +0000, glen herrmannsfeldt wrote:> In comp.dsp Allan Herriman <allanherriman@hotmail.com> wrote:>> 1. Generate an "ideal" reference waveform. Use floating point > (but use it carefully). > > My choice would be fixed point. > > With fixed point, you know exactly how the rounding is done, and it is > done independent of the size of the values at any point in the > computation. You could, for example, use 64 bit fixed point instead of > 64 bit floating point.Rickman appears to be writing a testbench in VHDL. If that is the case, he already has double precision floating point trig functions built in to his simulator (in package ieee.math_real). To use fixed point would be to reimplement and verify the trig functions from scratch - a task that is possibly harder than the original problem he is trying to solve. In general though, I do take your point about the rounding. I would also hazard a guess that Rickman is outputting samples from his testbench and then using a standalone FFT package (outside the VHDL simulation environment) instead of trying to code the FFT in VHDL. I guess this will probably only use floating point. I was thinking about the size of the FFT. The DDS is an FSM. The output is periodic. It's possible to match the number of points in the FFT to the number of states in the FSM, completely eliminating spectral leakage due to windowing. But I suspect he's using a 32 bit phase accumulator, which would rule out this approach. (How big can FFTs get these days? The largest I've ever done had 2**19 complex points, but that was last century on a Sparc.) Regards, Allan
Reply by ●December 21, 20142014-12-21
On 12/20/2014 11:33 PM, Allan Herriman wrote:> On Sat, 20 Dec 2014 19:43:33 +0000, glen herrmannsfeldt wrote: > >> In comp.dsp Allan Herriman <allanherriman@hotmail.com> wrote: > >>> 1. Generate an "ideal" reference waveform. Use floating point >> (but use it carefully). >> >> My choice would be fixed point. >> >> With fixed point, you know exactly how the rounding is done, and it is >> done independent of the size of the values at any point in the >> computation. You could, for example, use 64 bit fixed point instead of >> 64 bit floating point. > > Rickman appears to be writing a testbench in VHDL. If that is the case, > he already has double precision floating point trig functions built in to > his simulator (in package ieee.math_real). To use fixed point would be > to reimplement and verify the trig functions from scratch - a task that > is possibly harder than the original problem he is trying to solve.A reasonable assumption although I couldn't find info that said that reals were double precision (64 bit). In fact, the info I found said they are only assured to be 32 bit, single precision. Is that wrong? If the VHDL floating point only has a 24 bit mantissa the resolution is only slightly better than the signals I am attempting to measure. In that case I would consider writing out the NCO data to a file for processing in some other environment. In fact, maybe I should do that anyway for multiple reasons. I understand there are open source packages similar to Matlab. I may try using one of these.> In general though, I do take your point about the rounding. > > I would also hazard a guess that Rickman is outputting samples from his > testbench and then using a standalone FFT package (outside the VHDL > simulation environment) instead of trying to code the FFT in VHDL. I > guess this will probably only use floating point. > > > I was thinking about the size of the FFT. The DDS is an FSM. The output > is periodic. It's possible to match the number of points in the FFT to > the number of states in the FSM, completely eliminating spectral leakage > due to windowing. But I suspect he's using a 32 bit phase accumulator, > which would rule out this approach. (How big can FFTs get these days? > The largest I've ever done had 2**19 complex points, but that was last > century on a Sparc.)Once I find the spurs in an FFT, I can narrow down the search to selected bins and use a DFT. -- Rick
