Hello folks, Just a quickie: Have you ever come across or can you think of a reason why you would have an FIR impulse response that started with one or more zeros? Cheers, Ken -- To reply by email, please remove the _MENOWANTSPAM from my email address.
Impulse response starting with zeros?
Started by ●July 14, 2003
Reply by ●July 14, 20032003-07-14
"Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote in message news:beudc9$iqd$1@dennis.cc.strath.ac.uk...> > Hello folks, > > Just a quickie: > > Have you ever come across or can you think of a reason why you would havean> FIR impulse response that started with one or more zeros? > > Cheers, > > Ken > -- > To reply by email, please remove the _MENOWANTSPAM from my email address.Hi Ken, Yes - very often (when your state initial conditions are zero that is...) It takes some number of samples to push your initial conditions and startup transients through the filter structure. Often this is refered to as the filter's group delay. hth, Steve
Reply by ●July 14, 20032003-07-14
"Steve Conahan" <sconahan@mathworks.com> wrote in message news:beueuo$llj$1@ginger.mathworks.com...> "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote in message > news:beudc9$iqd$1@dennis.cc.strath.ac.uk... > > > > Hello folks, > > > > Just a quickie: > > > > Have you ever come across or can you think of a reason why you wouldhave> an > > FIR impulse response that started with one or more zeros? > > > > Cheers, > > > > Ken > > -- > > To reply by email, please remove the _MENOWANTSPAM from my emailaddress.> > Hi Ken, > > Yes - very often (when your state initial conditions are zero that is...) > > It takes some number of samples to push your initial conditions andstartup> transients through the filter structure. Often this is refered to as the > filter's group delay. > > hth, > Steve >(replying to myself - must be Monday morning...) ;-) Actually, thinking more clearly now, having an initial zero value could be a *rare* thing for an FIR filter unless the initial "multiply and accumulate" happens to equal exactly zero. For an impulse resp, this would happen if your initial happen to "balance things out" in the MAC. So your initial conditions would have to be non-zero. Another reason (if you are measuring hardware outputs) in an FPGA or ASIC implementation is that you might just have some additional initial hardware latency to worry about before seeing valid outputs, so that could possibly explain it(?) How is the filter implemented? Cheers, Steve
Reply by ●July 14, 20032003-07-14
> > Hi Ken, > > > > Yes - very often (when your state initial conditions are zero thatis...)> > > > It takes some number of samples to push your initial conditions and > startup > > transients through the filter structure. Often this is refered to asthe> > filter's group delay. > > > > hth, > > Steve > > > > (replying to myself - must be Monday morning...) ;-) > > Actually, thinking more clearly now, having an initial zero value could bea> *rare* thing for an FIR filter unless the initial "multiply andaccumulate"> happens to equal exactly zero. > > For an impulse resp, this would happen if your initial happen to "balance > things out" in the MAC. So your initial conditions would have to be > non-zero. Another reason (if you are measuring hardware outputs) in anFPGA> or ASIC implementation is that you might just have some additional initial > hardware latency to worry about before seeing valid outputs, so that could > possibly explain it(?) > > How is the filter implemented? > > Cheers, > SteveHi Steve, Thanks for your replies. I should explain further: I don't have a problem with unexpected zero outputs from my filter (it is in VHDL btw and works just fine!) - I was wondering if there were any mathematical/DSP system design level reasons for a dsp engineer to define an FIR filter response with one or more zeros at the start of the filter weights. Hope that clarifies things a bit! Cheers, Ken
Reply by ●July 14, 20032003-07-14
"Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote in message news:beuh7o$jpt$1@dennis.cc.strath.ac.uk...> > > Hi Ken, > > > > > > Yes - very often (when your state initial conditions are zero that > is...) > > > > > > It takes some number of samples to push your initial conditions and > > startup > > > transients through the filter structure. Often this is refered to as > the > > > filter's group delay. > > > > > > hth, > > > Steve > > > > > > > (replying to myself - must be Monday morning...) ;-) > > > > Actually, thinking more clearly now, having an initial zero value couldbe> a > > *rare* thing for an FIR filter unless the initial "multiply and > accumulate" > > happens to equal exactly zero. > > > > For an impulse resp, this would happen if your initial happen to"balance> > things out" in the MAC. So your initial conditions would have to be > > non-zero. Another reason (if you are measuring hardware outputs) in an > FPGA > > or ASIC implementation is that you might just have some additionalinitial> > hardware latency to worry about before seeing valid outputs, so thatcould> > possibly explain it(?) > > > > How is the filter implemented? > > > > Cheers, > > Steve > > > Hi Steve, > > Thanks for your replies. > > I should explain further: > > I don't have a problem with unexpected zero outputs from my filter (it isin> VHDL btw and works just fine!) - I was wondering if there were any > mathematical/DSP system design level reasons for a dsp engineer to definean> FIR filter response with one or more zeros at the start of the filter > weights. > > Hope that clarifies things a bit! > > Cheers, > > KenHi Ken, I don't know of any strictly mathematical/theoretical reason why the zero outputs would be there (except for when the initial conditions are such that the initial output after the MAC just so happens to equal zero). However I very well could be mistaken... However from a sytem level design perspective, I would hope that a good DSP system designer would take the additional hardware latency into account in the filter design (e.g. by adding simulated sample delays at the filter outputs as needed during the system design and later implementation process iteration loops) before going through the pain/cost of finding this out too late in the design cycle (e.g. based on bad/incorrect latency assumptions regarding the final hardware implementation). This can be tricky to model - as it sounds like you know already. Cheers, Steve
Reply by ●July 14, 20032003-07-14
"Steve Conahan" <sconahan@mathworks.com> wrote in message news:beuiih$soh$1@ginger.mathworks.com...> "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote in message > news:beuh7o$jpt$1@dennis.cc.strath.ac.uk... > > > > Hi Ken, > > > > > > > > Yes - very often (when your state initial conditions are zero that > > is...) > > > > > > > > It takes some number of samples to push your initial conditions and > > > startup > > > > transients through the filter structure. Often this is refered toas> > the > > > > filter's group delay. > > > > > > > > hth, > > > > Steve > > > > > > > > > > (replying to myself - must be Monday morning...) ;-) > > > > > > Actually, thinking more clearly now, having an initial zero valuecould> be > > a > > > *rare* thing for an FIR filter unless the initial "multiply and > > accumulate" > > > happens to equal exactly zero. > > > > > > For an impulse resp, this would happen if your initial happen to > "balance > > > things out" in the MAC. So your initial conditions would have to be > > > non-zero. Another reason (if you are measuring hardware outputs) inan> > FPGA > > > or ASIC implementation is that you might just have some additional > initial > > > hardware latency to worry about before seeing valid outputs, so that > could > > > possibly explain it(?) > > > > > > How is the filter implemented? > > > > > > Cheers, > > > Steve > > > > > > Hi Steve, > > > > Thanks for your replies. > > > > I should explain further: > > > > I don't have a problem with unexpected zero outputs from my filter (itis> in > > VHDL btw and works just fine!) - I was wondering if there were any > > mathematical/DSP system design level reasons for a dsp engineer todefine> an > > FIR filter response with one or more zeros at the start of the filter > > weights. > > > > Hope that clarifies things a bit! > > > > Cheers, > > > > Ken > > Hi Ken, > > I don't know of any strictly mathematical/theoretical reason why the zero > outputs would be there (except for when the initial conditions are suchthat Steve, I think you didn't understand the original question.... He wants to know if there is a reason to have the first (or first few) coeffs of the FIR filter set as zero (not the filter outputs). Anyways, I have come across some filter designs (using some kind of filter design program) that gave me filter coeffs where the first coeff was a zero. Perhaps it was really small and I used quantization - I don't remember. If it is indeed zero, I think you can safely ignore that and reduce your filter taps by 1. However, If you are trying to fit your design to an algorithm that takes advantage of a particular filter order (say odd # of coeffs), you may want to retain the zero - this is the one reason I can think of. Cheers Bhaskar> the initial output after the MAC just so happens to equal zero). HoweverI> very well could be mistaken... > > However from a sytem level design perspective, I would hope that a goodDSP> system designer would take the additional hardware latency into account in > the filter design (e.g. by adding simulated sample delays at the filter > outputs as needed during the system design and later implementationprocess> iteration loops) before going through the pain/cost of finding this outtoo> late in the design cycle (e.g. based on bad/incorrect latency assumptions > regarding the final hardware implementation). This can be tricky tomodel -> as it sounds like you know already. > > Cheers, > Steve > > >
Reply by ●July 14, 20032003-07-14
Ken wrote:>...> > I don't have a problem with unexpected zero outputs from my filter (it is in > VHDL btw and works just fine!) - I was wondering if there were any > mathematical/DSP system design level reasons for a dsp engineer to define an > FIR filter response with one or more zeros at the start of the filter > weights. > > Hope that clarifies things a bit! > > Cheers, > > KenWith a by-rote windowed-sinc design, if the window has an initial zero, and the piece of the sinc that'd being windowed has a zero as its next coefficient, there could be a pair of zeros at each end. A heads-up designer will omit those, making the filter four taps shorter. You can posit other cases with half-band filters and Hilbert transformers. Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Reply by ●July 14, 20032003-07-14
On Mon, 14 Jul 2003 16:06:26 +0100, Ken wrote:> Have you ever come across or can you think of a reason why you would > have an FIR impulse response that started with one or more zeros?I can think of a few reasons, but they all get back to the effect. Zeros at the beginning of the impulse response will delay the signal. Adding a delay here can sometimes be handy. Consider a system with hardware FIR filters where the coefficients are programmable. If you need to add a delay somewhere, it is often easiest to add them to the filters. -- Matthew Donadio (m.p.donadio@ieee.org)
Reply by ●July 14, 20032003-07-14
Ken, Could also use it to add a short in-path delay without handling extra delay explicitly, perhaps to match multiple path delays. Dirk Dirk A. Bell DSP Consultant "Jerry Avins" <jya@ieee.org> wrote in message news:3F12D543.6A7084C1@ieee.org...> Ken wrote: > > > ... > > > > I don't have a problem with unexpected zero outputs from my filter (itis in> > VHDL btw and works just fine!) - I was wondering if there were any > > mathematical/DSP system design level reasons for a dsp engineer todefine an> > FIR filter response with one or more zeros at the start of the filter > > weights. > > > > Hope that clarifies things a bit! > > > > Cheers, > > > > Ken > > With a by-rote windowed-sinc design, if the window has an initial zero, > and the piece of the sinc that'd being windowed has a zero as its next > coefficient, there could be a pair of zeros at each end. A heads-up > designer will omit those, making the filter four taps shorter. You can > posit other cases with half-band filters and Hilbert transformers. > > Jerry > -- > Engineering is the art of making what you want from things you can get. > �����������������������������������������������������������������������
Reply by ●July 14, 20032003-07-14
>Consider a system with hardware FIR filters where the coefficients are >programmable. If you need to add a delay somewhere, it is often easiest >to add them to the filters.Exactly. An example can be found at http://grassomusic.de/e/phaseeq2.htm#delay Uli -- ------- http://grassomusic.de -------
