clock system design on ADSP2191M

Hello,

i want to use a single clock to control the ADSP2191M
and an audio codec with a 24.576MHz quartz.
Fortunately, the 2191 has a PLL that can do 6.5x so
it can reach 159.744MHz, which is pretty near
the maximum 160MHz core frequency.

But then, things get complicated.
it seems that CLKOUT (provided by the 2191)
outputs the PLL's frequency, but i want to get
the "input" frequency of 24.576MHz so it can go
to the CODEC's MCLK pin. And i don't want
to use an external clock divider because
this design's goal is simplicity and economy.

Other solutions : use an external quartz osc. but
i don't know any and it would add another part
that could be difficult to get. Integrated oscillators
at this frequency are difficult for me to get as well.
Another way would be to get the Xtal output and
buffer it, but that could be really naughty
and i'm not good at oscillators, this could prevent
it from working as expected.

Please, can anybody give me advices ?
Is there an option in the configuration
bits that i have overlooked ?

Regards,
YG

YG <whygee@f-cpu.org> wrote in news:3EFF58CB.30906@f-cpu.org:

> Hello,
> 
> i want to use a single clock to control the ADSP2191M
> and an audio codec with a 24.576MHz quartz.
> Fortunately, the 2191 has a PLL that can do 6.5x so
> it can reach 159.744MHz, which is pretty near
> the maximum 160MHz core frequency.
> 
> But then, things get complicated.
> it seems that CLKOUT (provided by the 2191)
> outputs the PLL's frequency, but i want to get
> the "input" frequency of 24.576MHz so it can go
> to the CODEC's MCLK pin. And i don't want
> to use an external clock divider because
> this design's goal is simplicity and economy.
> 
> Other solutions : use an external quartz osc. but
> i don't know any and it would add another part
> that could be difficult to get. Integrated oscillators
> at this frequency are difficult for me to get as well.
> Another way would be to get the Xtal output and
> buffer it, but that could be really naughty
> and i'm not good at oscillators, this could prevent
> it from working as expected.
> 
> Please, can anybody give me advices ?
> Is there an option in the configuration
> bits that i have overlooked ?
> 
> Regards,
> YG
> 
> 

Use a 1nF capacitor from Xtal (pin 133 - QFP) to a 74VHC or AHC inverter.  
Tie a 100K resistor from input to output of the inverter. 

The output of the inverter is your codec clock. You should add a small 
resistor (33 Ohm) near the inverter output if you are driving more than a 
few inches.

Use a ground plane and 3.3V Power plane or the PLL may not work well (or 
at all).

The other alternative would be to use a codec that can supply the clock 
to the DSP. Clock jitter contributes to noise is a sigma delta converter 
and the codec's clock circuit will be a better oscillator. Note that not 
all codecs will let you use its clock while the part is in reset (AC-97 
codecs are one example), so this may not be an option. 

We have a dspstak 219x board that you might be interested in. It 
addresses all these issues. 



-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com

In article <3EFF58CB.30906@f-cpu.org>, whygee@f-cpu.org says...
> Hello,
> 
> i want to use a single clock to control the ADSP2191M
> and an audio codec with a 24.576MHz quartz.
> Fortunately, the 2191 has a PLL that can do 6.5x so
> it can reach 159.744MHz, which is pretty near
> the maximum 160MHz core frequency.
> 
> But then, things get complicated.
> it seems that CLKOUT (provided by the 2191)
> outputs the PLL's frequency, but i want to get
> the "input" frequency of 24.576MHz so it can go
> to the CODEC's MCLK pin. And i don't want
> to use an external clock divider because
> this design's goal is simplicity and economy.
> 
> Other solutions : use an external quartz osc. but
> i don't know any and it would add another part
> that could be difficult to get. Integrated oscillators
> at this frequency are difficult for me to get as well.
> Another way would be to get the Xtal output and
> buffer it, but that could be really naughty
> and i'm not good at oscillators, this could prevent
> it from working as expected.
> 
> Please, can anybody give me advices ?
> Is there an option in the configuration
> bits that i have overlooked ?
> 
> Regards,
> YG
> 
> 

NB there are 2 variants of the 2191M.  K-Grade (160 MIPS) and B-Grade 
(140 MIPS).  Check out page 19 of the datasheet.  I was trying to clock 
mine to 160 till I peered at the part on the proto sitting on my desk 
and noticed the "BST" extension.

Theres not alot of choice for the CLKOUT pin (HCLK).  Its either 
disabled, equal to the core clock (CCLK) or 1/2 the core clock, 
depending on IOSEL bit in the PLLCTL register.  See p B-15 in the 
databook. Note that there's plenty of choice for the core clock (divide 
frequency bit and 1 - 32 multiplier)

As far as I know, if you really want to use CLKOUT and the same crystal, 
and you really want to get 24.576 MHz out of CLKOUT, then you need to 
clock your core at 50 MIPS, then use IOSEL bit to set CLKOUT back to 25 
MHz. Although it doesn't sound like you'd be happy to run it at 50 MIPS.

I think your best solution is to drive the codec with the same crystal 
directly.  Just connect the MCLK input of the codec to the XTAL side of 
the crystal driving the 2191. Thats pretty simple and economical ;o)

Spiro

-- 


http://www.mobilecomms.com.au
http://www.nexiondata.com

hi !

Spiro wrote:
> In article <3EFF58CB.30906@f-cpu.org>, whygee@f-cpu.org says...
> 
>>Hello,

<snip>

> NB there are 2 variants of the 2191M.  K-Grade (160 MIPS) and B-Grade 
> (140 MIPS).  Check out page 19 of the datasheet.  I was trying to clock 
> mine to 160 till I peered at the part on the proto sitting on my desk 
> and noticed the "BST" extension.

no worries here ;-)

> Theres not alot of choice for the CLKOUT pin (HCLK).  Its either 
> disabled, equal to the core clock (CCLK) or 1/2 the core clock, 
> depending on IOSEL bit in the PLLCTL register.  See p B-15 in the 
> databook. Note that there's plenty of choice for the core clock (divide 
> frequency bit and 1 - 32 multiplier)

mmmh then this solution is not possible.

> As far as I know, if you really want to use CLKOUT and the same crystal, 
> and you really want to get 24.576 MHz out of CLKOUT, then you need to 
> clock your core at 50 MIPS, then use IOSEL bit to set CLKOUT back to 25 
> MHz. Although it doesn't sound like you'd be happy to run it at 50 MIPS.

that could be possible, but not desired :-/

> I think your best solution is to drive the codec with the same crystal 
> directly.  Just connect the MCLK input of the codec to the XTAL side of 
> the crystal driving the 2191. Thats pretty simple and economical ;o)

This is probably going to create many problems, i think.
i'll probably use a pair of MAX541, because SPORT-based solutions
with "classical" codecs are really annoying, for the clock setup and
the configuration .... I am investigating the AD73322 but i'll probably
drop it.

> Spiro

In article <3EFF8F91.2010404@f-cpu.org>, whygee@f-cpu.org says...

> > I think your best solution is to drive the codec with the same crystal 
> > directly.  Just connect the MCLK input of the codec to the XTAL side of 
> > the crystal driving the 2191. Thats pretty simple and economical ;o)
> 
> This is probably going to create many problems, i think.
> i'll probably use a pair of MAX541, because SPORT-based solutions
> with "classical" codecs are really annoying, for the clock setup and
> the configuration .... I am investigating the AD73322 but i'll probably
> drop it.

Hi,

We do this on our design and have done so for a few years.  No problems 
at all (for our application).  What Al said in his post sounds like the 
right way to do it perfectly.  To make it simple, we take a shortcut, 
then test it to see if it works within the spec of our application.  We 
have driven both 73322's and 73311's directly from the same crystal, and 
for our frequencies of interest (audio) we are getting about -70 to -80 
dB s/n (which turns out to be far more accurate than other parts of our 
signal path).  It depends also of course on other design decisions too, 
like the quality/spec of you anti aliasing filter, whether you are using 
the codec in differential input mode, whether you have a switcher in the 
same vicinity, how close you analog input circuit lies to any digital 
lines, how close the h/w designer was able to get the decoupling caps to 
the dsp/codec etc, etc, all the regular noise stuff,

Spiro

-- 
http://www.mobilecomms.com.au
http://www.nexiondata.com

YG <whygee@f-cpu.org> wrote in news:3EFF8F91.2010404@f-cpu.org:

> hi !
> 
> Spiro wrote:
>> In article <3EFF58CB.30906@f-cpu.org>, whygee@f-cpu.org says...
>> 
>>>Hello,
> 
><snip>
> 
>> NB there are 2 variants of the 2191M.  K-Grade (160 MIPS) and B-Grade
>> (140 MIPS).  Check out page 19 of the datasheet.  I was trying to
>> clock mine to 160 till I peered at the part on the proto sitting on
>> my desk and noticed the "BST" extension.
> 

The 140 MHz part is specified for industrial temp rang, the 160M part is 
commercial temp range. They cost the same. They differ only in the ADI's 
promise of performance and the marking on the part. There really isn't any 
difference and I would guess that if you tried 10,000 pieces of either 
part, you would never see any difference.

Using this part at 160M means your layout was done correctly. The PLL is 
powered from the 3.3V I/O supply. My first two layer version did not work 
even though the 3.3V routing was done with fat traces and with good 
bypassing. All my multilayer designs have worked well at 160M.



-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com