HELP : IIR in an FPGA

Hello and thank you for reading my post !

I would like to design an IIR filter in a FPGA. It will be a 16-order 
filter, made with 8 second-order sections.

The signal to filter is 24 bit wide and I need those 24 bits of precision.

My question is : how many bits do I need at the outputs of my multiplier 
tu be sure that I still have 24 bits of precision at the output ?

Well, if we suppose that my coefficients are 16 bits wide (I hope it is 
wide enough), and the datas are 24, this makes an output of 40 bits... 
but it is an IIR, so I may need a 40 bits adder, then I will need to 
redesign one input of my multipliers for 40 bits.... but a multiplier of 
40*16 bits really takes a lot of area in the FPGA .... !

Any help would be much appreciated.

Thanks in advance !

Sam

Sam wrote:
> Hello and thank you for reading my post !
> 
> I would like to design an IIR filter in a FPGA. It will be a 16-order 
> filter, made with 8 second-order sections.
> 
> The signal to filter is 24 bit wide and I need those 24 bits of precision.
> 
> My question is : how many bits do I need at the outputs of my multiplier 
> tu be sure that I still have 24 bits of precision at the output ?
> 
> Well, if we suppose that my coefficients are 16 bits wide (I hope it is 
> wide enough), and the datas are 24, this makes an output of 40 bits... 
> but it is an IIR, so I may need a 40 bits adder, then I will need to 
> redesign one input of my multipliers for 40 bits.... but a multiplier of 
> 40*16 bits really takes a lot of area in the FPGA .... !
> 
> Any help would be much appreciated.
> 
> Thanks in advance !
> 
> Sam

Your data and coefficients fit suspiciously well into integer multiples 
of 8 -- is this necessary, or is it just what you're used to from 
whatever processor you've been using?  Also, what FPGA are you using? 
Both Xilinx and Altera, and probably everyone else by now, are building 
multiplier blocks into their stuff.

You can see if your coefficients are wide enough by truncating them then 
checking the transfer function of your IIR.  If it's still close enough 
then you're OK with that coefficient value.  You can see if your 
intermediate data is wide enough by testing your system for noise 
sensitivity at each spot where you truncate.  I usually assume that the 
noise will be as big as the data that I'm cutting off (i.e. if I 
truncate to 30 bits then I assume that the noise is 2^{-31}) and I 
assume it's at the worst possible frequency.  In general, though, if you 
have to make the coefficient that deep then you need to make the 
intermediate result wide enough to contain the result.

If you _do_ need deep coefficients it's likely that you have numbers 
that are close to 1 (or possibly 2); if that's the case you can use the 
distributive property to reduce the size of your multiplier.  For 
example, if you have a coefficient equal to 0.9998 that's equal to 1 - 
0.0002.  So instead of using a 16-bit multiply to capture the 0.9998, 
you use a three-bit multiplier to capture 0.0002 = 2^{-16} * 13 and 
calculate y = x - 0.0002x.  This won't ease your additions at all, but 
it will make your multipliers smaller.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Well, I think I'll use a Spartan 3 FPGA... I'm trying to design the 
filter, then see what exact device fits it.

Yes, I know altera and xilinx build multiplier blocks (as 18x18 bit in 
spartan3 or furute cyclone2), but if I need a 40*16 multiplier, and 6 
multipliers by second order section (5 for the coeffs and one for the 
scaling), I will not be able to get a higher order than 4 or 8 ...

Thank you for your hints about truncating ... but, how do you test the 
system with noise at the worse frequency ? What is this frequency ?

I don't need especially deep filter coefficients (as a0, a1, b0, b1, 
etc.), but I need a good data precision... I would like my system to 
have about 120 dB of dynamic range, so I don't want to reduce it by 
truncating too much.

thanks !

Sam

Sam wrote:

> 
> Well, I think I'll use a Spartan 3 FPGA... I'm trying to design the 
> filter, then see what exact device fits it.
> 
> Yes, I know altera and xilinx build multiplier blocks (as 18x18 bit in 
> spartan3 or furute cyclone2), but if I need a 40*16 multiplier, and 6 
> multipliers by second order section (5 for the coeffs and one for the 
> scaling), I will not be able to get a higher order than 4 or 8 ...
> 
> Thank you for your hints about truncating ... but, how do you test the 
> system with noise at the worse frequency ? What is this frequency ?
> 
> I don't need especially deep filter coefficients (as a0, a1, b0, b1, 
> etc.), but I need a good data precision... I would like my system to 
> have about 120 dB of dynamic range, so I don't want to reduce it by 
> truncating too much.
> 
> thanks !
> 
> Sam

You don't need or want to do a physical test, at least initially.  What 
you do is model the system as a block diagram and calculate the system 
transfer function from the truncation point to the output.  Then plot 
that transfer function's magnitude vs. frequency - the worst frequency, 
and the magnitude of the error, will be immediately apparent.

This is a subject that's well treated in any signal processing text that 
treats DSP.  Rick Lyon's "Understanding Digital Signal Processing" 
touches on this and Oppenheim & Shafer's "Digital Signal Processing" has 
an entire chapter on the subject.  There are more, but those are the two 
that I have references for at the moment.  You may want to look at 
http://www.wescottdesign.com/articles/BlockDiagrams/BlockDiagrams.html, 
which has the method for finding the transfer function from an arbitrary 
noise injection point in a block diagram to the output.  If you're just 
cascading 1st and 2nd order sections (which is what you _should_ be 
doing!) then it ought to be fairly easy.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com