Pipelined ADCs

I am trying to locate tutorial information on pipelined ADCs, without any
success as yet. I would very grateful for any pointers that readers may be able
to provide.
Many thanks
John Ferguson

jrferguson@aol.com (Jrferguson) writes:

> I am trying to locate tutorial information on pipelined ADCs, without any
> success as yet. I would very grateful for any pointers that readers may be able
> to provide.

Pipelines are to paralellize things like instruction accesses,
decoding, execution, etc. None of these occur in an A/D.

Are you thinking perhaps of multiplexing A/Ds that use multiple samplers
to get higher sampling rates?
-- 
%  Randy Yates                  % "So now it's getting late,
%% Fuquay-Varina, NC            %    and those who hesitate
%%% 919-577-9882                %    got no one..."
%%%% <yates@ieee.org>           % 'Waterfall', *Face The Music*, ELO
http://home.earthlink.net/~yatescr

Randy Yates wrote:
> jrferguson@aol.com (Jrferguson) writes:
> 
> 
>>I am trying to locate tutorial information on pipelined ADCs, without any
>>success as yet. I would very grateful for any pointers that readers may be able
>>to provide.
> 
> 
> Pipelines are to paralellize things like instruction accesses,
> decoding, execution, etc. None of these occur in an A/D.
> 
> Are you thinking perhaps of multiplexing A/Ds that use multiple samplers
> to get higher sampling rates?

Newer high-speed ADCs _are_ pipelined, with a new result popping out 
four to six clock cycles after the corresponding sample -- so a 40MS/s 
ADC will deliver a new conversion every 25ns, but that conversion will 
be delivered 100ns after the sample was taken.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Jrferguson wrote:

> I am trying to locate tutorial information on pipelined ADCs, without any
> success as yet. I would very grateful for any pointers that readers may be able
> to provide.
> Many thanks
> John Ferguson

You might want to do a search on data sheets and application notes -- 
that's the kind of thing that some app engineer somewhere would feel 
motivated to write a paper on.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

On Fri, 24 Dec 2004 15:25:23 GMT, Randy Yates <yates@ieee.org> wrote:

>jrferguson@aol.com (Jrferguson) writes:
>
>> I am trying to locate tutorial information on pipelined ADCs, without any
>> success as yet. I would very grateful for any pointers that readers may be able
>> to provide.
>
>Pipelines are to paralellize things like instruction accesses,
>decoding, execution, etc. None of these occur in an A/D.
>
>Are you thinking perhaps of multiplexing A/Ds that use multiple samplers
>to get higher sampling rates?

Randy, you seem to have missed a revolution in high speed ADC design
from, umm, about a decade ago.

Pipelined converters allow high resolution (12-14 bits) at high sample
rates (~100Msps).  No other converter architecture comes close (Flash
can be faster, but only at low resolutions).  The development of
pipelined converters has enabled the ADC to move "closer to the
antenna" in digital radio designs.  (I'm not sure which was the cause,
and which was the effect - pipelined converters and digital radio go
hand-in-hand.)


The problem with a Flash converter is that the number of comparators
increases exponentially with the number of bits.  This limits the
number of bits to about 10.

To increase the number of bits further, we can use N (typically 2 or
3) lower resolution flash converters.  The output of the first
converter is sent to a DAC.  The output of the DAC is subtracted from
the input signal, and this residue is then amplified and sent to the
next identical stage in the pipeline.  Typically there is a sample and
hold between each stage in the pipeline.

This results in a circuit size that grows roughly linearly with the
number of bits, instead of exponentially.

The individual Flash converters and DACs in the pipeline stages don't
need many bits (typically 6), but the first stage needs to have an
*accuracy* determined by the total number of bits being generated.

About the only disadvantage of pipelined converters is the pipeline
delay, which may be an issue if the ADC is in a feedback loop.


The obvious place to look for information about them is on the
manufacturers' web sites.
http://www.analog.com/en/subCat/0,2879,760%255F788%255F0%255F%255F0%255F,00.html
http://focus.ti.com/paramsearch/docs/producttree.tsp?familyId=82&templateId=4&family=analog&path=default_home

etc.

Regards,
Allan

Here's a good example:

http://www.analog.com/en/prod/0%2C%2CAD6645%2C00.html

Regards,
Allan

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> writes:

> On Fri, 24 Dec 2004 15:25:23 GMT, Randy Yates <yates@ieee.org> wrote:
>
>>jrferguson@aol.com (Jrferguson) writes:
>>
>>> I am trying to locate tutorial information on pipelined ADCs, without any
>>> success as yet. I would very grateful for any pointers that readers may be able
>>> to provide.
>>
>>Pipelines are to paralellize things like instruction accesses,
>>decoding, execution, etc. None of these occur in an A/D.
>>
>>Are you thinking perhaps of multiplexing A/Ds that use multiple samplers
>>to get higher sampling rates?
>
> Randy, you seem to have missed a revolution in high speed ADC design
> from, umm, about a decade ago.
>
> Pipelined converters allow high resolution (12-14 bits) at high sample
> rates (~100Msps).  No other converter architecture comes close (Flash
> can be faster, but only at low resolutions).  The development of
> pipelined converters has enabled the ADC to move "closer to the
> antenna" in digital radio designs.  (I'm not sure which was the cause,
> and which was the effect - pipelined converters and digital radio go
> hand-in-hand.)
>
>
> The problem with a Flash converter is that the number of comparators
> increases exponentially with the number of bits.  This limits the
> number of bits to about 10.
>
> To increase the number of bits further, we can use N (typically 2 or
> 3) lower resolution flash converters.  The output of the first
> converter is sent to a DAC.  The output of the DAC is subtracted from
> the input signal, and this residue is then amplified and sent to the
> next identical stage in the pipeline.  Typically there is a sample and
> hold between each stage in the pipeline.
>
> This results in a circuit size that grows roughly linearly with the
> number of bits, instead of exponentially.
>
> The individual Flash converters and DACs in the pipeline stages don't
> need many bits (typically 6), but the first stage needs to have an
> *accuracy* determined by the total number of bits being generated.
>
> About the only disadvantage of pipelined converters is the pipeline
> delay, which may be an issue if the ADC is in a feedback loop.

It is clear that I had a gap in my understanding on this topic,
Allan. Thank you for giving me a heads-up and a quick education.

I also apologize to Jrferguson (and anyone else read and was misled)
for giving wrong information.

However, Allan, could I ask you to please do one thing? Refrain from
using the "umm" idiom when you write usenet posts unless your
intention is to disrepect the poster. 
-- 
%  Randy Yates                  % "She's sweet on Wagner-I think she'd die for Beethoven.
%% Fuquay-Varina, NC            %  She love the way Puccini lays down a tune, and
%%% 919-577-9882                %  Verdi's always creepin' from her room." 
%%%% <yates@ieee.org>           % "Rockaria", *A New World Record*, ELO   
http://home.earthlink.net/~yatescr

On Fri, 24 Dec 2004 17:33:39 GMT, Randy Yates <yates@ieee.org> wrote:

>It is clear that I had a gap in my understanding on this topic,
>Allan. Thank you for giving me a heads-up and a quick education.

I wish I had a nickel for every time I mis-spoke a quick answer like
that here.   Fortunately there are enough competent folks around here
to fix things quickly that the damage is usually minimal.  ;)

>I also apologize to Jrferguson (and anyone else read and was misled)
>for giving wrong information.

>However, Allan, could I ask you to please do one thing? Refrain from
>using the "umm" idiom when you write usenet posts unless your
>intention is to disrepect the poster. 

Actually, I use that device occassionally to indicate the opposite, as
in "well, I respect your opinion but I think in this case we may wish
to investigate the possibility of an error..."

Often the reader has as little clue about interpreting the intended
tone of what's written as the writer does about anticipating how it
will be interpreted.  


Eric Jacobsen
Minister of Algorithms, Intel Corp.
My opinions may not be Intel's opinions.
http://www.ericjacobsen.org

eric.jacobsen@ieee.org (Eric Jacobsen) writes:
> On Fri, 24 Dec 2004 17:33:39 GMT, Randy Yates <yates@ieee.org> wrote:
> [...]
>> However, Allan, could I ask you to please do one thing? Refrain from
>> using the "umm" idiom when you write usenet posts unless your
>> intention is to disrepect the poster. 
>
> Actually, I use that device occassionally to indicate the opposite, as
> in "well, I respect your opinion but I think in this case we may wish
> to investigate the possibility of an error..."

Interesting. 

> Often the reader has as little clue about interpreting the intended
> tone of what's written as the writer does about anticipating how it
> will be interpreted.  

It does seem to be a surprisingly-difficult thing to do!
-- 
%  Randy Yates                  % "I met someone who looks alot like you,
%% Fuquay-Varina, NC            %             she does the things you do, 
%%% 919-577-9882                %                     but she is an IBM."
%%%% <yates@ieee.org>           %        'Yours Truly, 2095', *Time*, ELO   
http://home.earthlink.net/~yatescr

Hi,

*A* decade? Try 3 decades. We used these things in the 1970s. They took 
several chips in a multi-chip hybrid package back then, but did 
basically the same thing. Of course, back then we considered 12 bits and 
a few mega-samples/second pretty neat. :-)

Regards,
Steve


Allan Herriman wrote:
> On Fri, 24 Dec 2004 15:25:23 GMT, Randy Yates <yates@ieee.org> wrote:
> 
> 
>>jrferguson@aol.com (Jrferguson) writes:
>>
>>
>>>I am trying to locate tutorial information on pipelined ADCs, without any
>>>success as yet. I would very grateful for any pointers that readers may be able
>>>to provide.
>>
>>Pipelines are to paralellize things like instruction accesses,
>>decoding, execution, etc. None of these occur in an A/D.
>>
>>Are you thinking perhaps of multiplexing A/Ds that use multiple samplers
>>to get higher sampling rates?
> 
> 
> Randy, you seem to have missed a revolution in high speed ADC design
> from, umm, about a decade ago.
> 
> Pipelined converters allow high resolution (12-14 bits) at high sample
> rates (~100Msps).  No other converter architecture comes close (Flash
> can be faster, but only at low resolutions).  The development of
> pipelined converters has enabled the ADC to move "closer to the
> antenna" in digital radio designs.  (I'm not sure which was the cause,
> and which was the effect - pipelined converters and digital radio go
> hand-in-hand.)
> 
> 
> The problem with a Flash converter is that the number of comparators
> increases exponentially with the number of bits.  This limits the
> number of bits to about 10.
> 
> To increase the number of bits further, we can use N (typically 2 or
> 3) lower resolution flash converters.  The output of the first
> converter is sent to a DAC.  The output of the DAC is subtracted from
> the input signal, and this residue is then amplified and sent to the
> next identical stage in the pipeline.  Typically there is a sample and
> hold between each stage in the pipeline.
> 
> This results in a circuit size that grows roughly linearly with the
> number of bits, instead of exponentially.
> 
> The individual Flash converters and DACs in the pipeline stages don't
> need many bits (typically 6), but the first stage needs to have an
> *accuracy* determined by the total number of bits being generated.
> 
> About the only disadvantage of pipelined converters is the pipeline
> delay, which may be an issue if the ADC is in a feedback loop.
> 
> 
> The obvious place to look for information about them is on the
> manufacturers' web sites.
> http://www.analog.com/en/subCat/0,2879,760%255F788%255F0%255F%255F0%255F,00.html
> http://focus.ti.com/paramsearch/docs/producttree.tsp?familyId=82&templateId=4&family=analog&path=default_home
> 
> etc.
> 
> Regards,
> Allan