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Please help me in understanding "Decimation filter"

Started by hswnetin September 10, 2004
Hi All,

I thank all of you, for your support, which I got previously. I am
hardware design engineer and working on sigma delta ADC. And my role
is to design decimation filter, basically I have to design a blocks
which converts single bit to multi bits output. I surveyed lots of
literature.

I referred "An Economical Class of Digital Filters for Decimation and
Interpolation" by Eugine B Hogenauer too. I could able to understand
the following things like, decimator receives single bit (or 2 or 3
bit output depending on modulator). And there are integrator stage and
comb stage. etc. I am unable to understand how the single bit is
converted to multi bits. I could not understand the concept of number
of stages. Also I could not understand the logic behind dropping of
bits after calculating the Bmax.

Please help me in understanding the issues in decimator filter.

Thanks in advance.

Regards,
hswnetin
hswnetin wrote:

> Hi All, > > I thank all of you, for your support, which I got previously. I am > hardware design engineer and working on sigma delta ADC. And my role > is to design decimation filter, basically I have to design a blocks > which converts single bit to multi bits output. I surveyed lots of > literature. > > I referred "An Economical Class of Digital Filters for Decimation and > Interpolation" by Eugine B Hogenauer too. I could able to understand > the following things like, decimator receives single bit (or 2 or 3 > bit output depending on modulator). And there are integrator stage and > comb stage. etc. I am unable to understand how the single bit is > converted to multi bits. I could not understand the concept of number > of stages. Also I could not understand the logic behind dropping of > bits after calculating the Bmax. > > Please help me in understanding the issues in decimator filter. > > Thanks in advance. > > Regards, > hswnetin
The modulator is constructed such that the average of the one bit output is equal to the DC value of the input -- so the simplest decimation filter would be something that sums the modulator output for a number of clocks, then takes the resulting register as the answer. For instance you could sum the modulator output for 4095 clocks and get a 12-bit output. Any time you implement a low-pass filter the instantaneous value of the input will have a relatively small effect on the output. This not only means that your filter storage elements need to have more precision than the input, it also means that some of that precision is valid at the output. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
hswnetin@yahoo.com (hswnetin) wrote in message news:<a4d4dd49.0409100158.333eb072@posting.google.com>...
> Hi All, > > I thank all of you, for your support, which I got previously. I am > hardware design engineer and working on sigma delta ADC. And my role > is to design decimation filter, basically I have to design a blocks > which converts single bit to multi bits output. I surveyed lots of > literature. > > I referred "An Economical Class of Digital Filters for Decimation and > Interpolation" by Eugine B Hogenauer too. I could able to understand > the following things like, decimator receives single bit (or 2 or 3 > bit output depending on modulator). And there are integrator stage and > comb stage. etc. I am unable to understand how the single bit is > converted to multi bits. I could not understand the concept of number > of stages. Also I could not understand the logic behind dropping of > bits after calculating the Bmax. >
The single bit is your LSB, and has the two values: +1 and -1. The integrator sums these bits for a multiple bit output. The larger (more bits) the integrator the higher the resolution, but at the cost of lower frequency response.
Hi all,

Thanks for your time and reply. I understood the following points from
your replies.

Understood point: Modulator produces single bit output either +1 or
-1, which decimator receives and process further.

Doubt 1: To add the stream of +1 and -1, why do we need multistage
integrators (as specified in Hogenauer paper)? Can't we use the single
stage integrator for the required resolution?
       
My thought: I am concentrating on implementation point of view. A
single counter (up/down counter) will do the job of integrator. As you
explained in previous posting example of integrating the over 4095
clocks need 12-bit accumulator. In the same way, 12-bit counter does
the job of integrator. Counter counts up when +1 is received and
counts down when -1 received.
	    
Doubt 2: Can't we use this approach? Are there any problems to do
this?

Please correct me.

Thanks and regards,
hswnetin



soar2morrow@yahoo.com (Tom Seim) wrote in message news:<6c71b322.0409101203.6c443a76@posting.google.com>...
> hswnetin@yahoo.com (hswnetin) wrote in message news:<a4d4dd49.0409100158.333eb072@posting.google.com>... > > Hi All, > > > > I thank all of you, for your support, which I got previously. I am > > hardware design engineer and working on sigma delta ADC. And my role > > is to design decimation filter, basically I have to design a blocks > > which converts single bit to multi bits output. I surveyed lots of > > literature. > > > > I referred "An Economical Class of Digital Filters for Decimation and > > Interpolation" by Eugine B Hogenauer too. I could able to understand > > the following things like, decimator receives single bit (or 2 or 3 > > bit output depending on modulator). And there are integrator stage and > > comb stage. etc. I am unable to understand how the single bit is > > converted to multi bits. I could not understand the concept of number > > of stages. Also I could not understand the logic behind dropping of > > bits after calculating the Bmax. > > > > The single bit is your LSB, and has the two values: +1 and -1. The > integrator sums these bits for a multiple bit output. The larger (more > bits) the integrator the higher the resolution, but at the cost of > lower frequency response.
hswnetin@yahoo.com (hswnetin) writes:

> Hi all, > > Thanks for your time and reply. I understood the following points from > your replies. > > Understood point: Modulator produces single bit output either +1 or > -1, which decimator receives and process further. > > Doubt 1: To add the stream of +1 and -1, why do we need multistage > integrators (as specified in Hogenauer paper)? Can't we use the single > stage integrator for the required resolution? > > My thought: I am concentrating on implementation point of view. A > single counter (up/down counter) will do the job of integrator. As you > explained in previous posting example of integrating the over 4095 > clocks need 12-bit accumulator. In the same way, 12-bit counter does > the job of integrator. Counter counts up when +1 is received and > counts down when -1 received. > > Doubt 2: Can't we use this approach? Are there any problems to do > this? > > Please correct me. > > Thanks and regards, > hswnetin
Hi hswnetin, I don't mean to be a buttinski, but allow me to suggest a perspective that may help you to understand how these animals work and what to design for. You've been thinking in the time domain. Instead, think in the frequency domain. Essentially a delta sigma A/D is a delta-sigma modulator followed by a downsampler. In order to know how to design the downsampler, you need to know what's coming out of the modulator. In the frequency domain, a coarsely-quantized signal (often just one bit) at a sample rate much greater than nyguist (M*Fs, M some oversampling ratio) will have an even amount of noise across the spectrum from 0 to M*Fs/2, and there is a bunch of it because the resolution of the quantizer is coarse. The delta sigma modulator shapes this noise so that the total amount (over the entire bandwidth from 0 to M*Fs/2) stays the same (even increases), but the amount from 0 to some bandwidth of interest B gets much less. So, your mission, Jim, should decide to accept it, is to filter out this nasty noise above B and thus provide a high SNR signal within the bandwidth B to your downstram elements. Caveat also that if you don't filter the stuff above B enough, it will alias down when you downsample. --RY
> > > > soar2morrow@yahoo.com (Tom Seim) wrote in message news:<6c71b322.0409101203.6c443a76@posting.google.com>... >> hswnetin@yahoo.com (hswnetin) wrote in message news:<a4d4dd49.0409100158.333eb072@posting.google.com>... >> > Hi All, >> > >> > I thank all of you, for your support, which I got previously. I am >> > hardware design engineer and working on sigma delta ADC. And my role >> > is to design decimation filter, basically I have to design a blocks >> > which converts single bit to multi bits output. I surveyed lots of >> > literature. >> > >> > I referred "An Economical Class of Digital Filters for Decimation and >> > Interpolation" by Eugine B Hogenauer too. I could able to understand >> > the following things like, decimator receives single bit (or 2 or 3 >> > bit output depending on modulator). And there are integrator stage and >> > comb stage. etc. I am unable to understand how the single bit is >> > converted to multi bits. I could not understand the concept of number >> > of stages. Also I could not understand the logic behind dropping of >> > bits after calculating the Bmax. >> > >> >> The single bit is your LSB, and has the two values: +1 and -1. The >> integrator sums these bits for a multiple bit output. The larger (more >> bits) the integrator the higher the resolution, but at the cost of >> lower frequency response.
-- % Randy Yates % "Watching all the days go by... %% Fuquay-Varina, NC % Who are you and who am I?" %%% 919-577-9882 % 'Mission (A World Record)', %%%% <yates@ieee.org> % *A New World Record*, ELO http://home.earthlink.net/~yatescr
Randy Yates wrote:
> hswnetin@yahoo.com (hswnetin) writes: > > >>Hi all, >> >>Thanks for your time and reply. I understood the following points from >>your replies. >> >>Understood point: Modulator produces single bit output either +1 or >>-1, which decimator receives and process further. >> >>Doubt 1: To add the stream of +1 and -1, why do we need multistage >>integrators (as specified in Hogenauer paper)? Can't we use the single >>stage integrator for the required resolution? >> >>My thought: I am concentrating on implementation point of view. A >>single counter (up/down counter) will do the job of integrator. As you >>explained in previous posting example of integrating the over 4095 >>clocks need 12-bit accumulator. In the same way, 12-bit counter does >>the job of integrator. Counter counts up when +1 is received and >>counts down when -1 received. >> >>Doubt 2: Can't we use this approach? Are there any problems to do >>this? >> >>Please correct me. >> >>Thanks and regards, >>hswnetin > > > Hi hswnetin, > > I don't mean to be a buttinski, but allow me to suggest a perspective > that may help you to understand how these animals work and what to > design for. > > You've been thinking in the time domain. Instead, think in the frequency > domain. > > Essentially a delta sigma A/D is a delta-sigma modulator followed by a > downsampler. In order to know how to design the downsampler, you need > to know what's coming out of the modulator. > > In the frequency domain, a coarsely-quantized signal > (often just one bit) at a sample rate much greater than nyguist (M*Fs, M > some oversampling ratio) will have an even amount of noise across the spectrum > from 0 to M*Fs/2, and there is a bunch of it because the resolution of the > quantizer is coarse. The delta sigma modulator shapes this noise so that > the total amount (over the entire bandwidth from 0 to M*Fs/2) stays the > same (even increases), but the amount from 0 to some bandwidth of interest > B gets much less. > > So, your mission, Jim, should decide to accept it, is to filter out > this nasty noise above B and thus provide a high SNR signal within > the bandwidth B to your downstram elements. > > Caveat also that if you don't filter the stuff above B enough, it > will alias down when you downsample. > > --RY > >
-- snip -- And the multiple filter approach is useful if your modulator is designed to shape the noise with a 2nd- or 3rd-order rolloff instead of a 1st-order rolloff. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Randy Yates wrote:

> In the frequency domain, a coarsely-quantized signal > (often just one bit) at a sample rate much greater than nyguist (M*Fs, M > some oversampling ratio) will have an even amount of noise across the spectrum > from 0 to M*Fs/2, and there is a bunch of it because the resolution of the > quantizer is coarse. The delta sigma modulator shapes this noise so that > the total amount (over the entire bandwidth from 0 to M*Fs/2) stays the > same (even increases), but the amount from 0 to some bandwidth of interest > B gets much less.
I always looked at the noise shaping aspect as separate from the sigma-delta modulator. A 1st order sigma-delta modulator (1-bit quantizer, delay,and comparator and 1st order loop filter) will provide a linear reduction in noise, proportional to 1/M(with the noise spread evenly from 0 to M*Fs/2). Using a 2nd or higher order loop filter provides the real "noise shaping" benefits mentioned above, that is deeper noise reduction in the band of interest and higher noise outside the band of interest, which can be removed in the decimation filter. -steve
Hi All,

Thanks for your replies. Now I will do little groundwork on analysis
in frequency domain. I will work on it, if i am not clear at any
point, I will post to group again. Before this can anyone tell me
about the spectrum of modulator output? Is it possible to see the
spectrum of output of the modulator? How to see the spectrum using
MATLAB? My basic doubt is producing the spectrum using single bit
data.

Please help me in this regard.

Thanks and regards,
hswnetin


Junk0 <junkaddress@comcast.net> wrote in message news:<OamdnYCAWcvgXd7cRVn-pQ@comcast.com>...
> Randy Yates wrote: > > > In the frequency domain, a coarsely-quantized signal > > (often just one bit) at a sample rate much greater than nyguist (M*Fs, M > > some oversampling ratio) will have an even amount of noise across the spectrum > > from 0 to M*Fs/2, and there is a bunch of it because the resolution of the > > quantizer is coarse. The delta sigma modulator shapes this noise so that > > the total amount (over the entire bandwidth from 0 to M*Fs/2) stays the > > same (even increases), but the amount from 0 to some bandwidth of interest > > B gets much less. > > I always looked at the noise shaping aspect as separate from > the sigma-delta modulator. A 1st order sigma-delta modulator > (1-bit quantizer, delay,and comparator and 1st order loop filter) > will provide a linear reduction in noise, proportional to 1/M(with > the noise spread evenly from 0 to M*Fs/2). Using a 2nd or higher > order loop filter provides the real "noise shaping" benefits mentioned > above, that is deeper noise reduction in the band of interest and > higher noise outside the band of interest, which can be removed in > the decimation filter. > > -steve
hswnetin@yahoo.com (hswnetin) writes:

> Hi All, > > Thanks for your replies. Now I will do little groundwork on analysis > in frequency domain. I will work on it, if i am not clear at any > point, I will post to group again. Before this can anyone tell me > about the spectrum of modulator output? Is it possible to see the > spectrum of output of the modulator? How to see the spectrum using > MATLAB? My basic doubt is producing the spectrum using single bit > data. > > Please help me in this regard. > > Thanks and regards, > hswnetin
Hi hswnetin, You can examine the spectrum of the one-bit modulator output in Matlab. If x is a vector of the modulator output values, then one way to examine the spectrum in Matlab is via "psd(x)". Note that since the modulator output is one bit, the elements of x will take on only two different values (e.g., +1/-1, 0x7FFF/0x80001, etc.). That's OK to input into the psd() routine and should give you exactly the spectrum you want to examine. If the output values are asymmetrical (e.g., 0/1), then you will have a DC offset, but that's not relevent to the upper part of the spectrum where the quantization noise will be. -- Randy Yates Sony Ericsson Mobile Communications Research Triangle Park, NC, USA randy.yates@sonyericsson.com, 919-472-1124
Randy Yates wrote:

> ... If the output values are asymmetrical (e.g., 0/1), then > you will have a DC offset, but that's not relevent to the upper part of the > spectrum where the quantization noise will be.
Hmmm... If there are no transitions at all, there will be lots of DC offset and no noise at all. Something doesn't hang together and at the moment, I don't see what. Jerry -- Engineering is the art of making what you want from things you can get. &#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;&#2013266095;