On 25.07.2015 18:41, Eric Jacobsen wrote: (snip)> In general one can always trade sample rate for ADC precision, i.e., > you can reduce the ADC precision by one bit if you increase the sample > rate by a factor of four. So to reduce a eight-bit converter to > one-bit, you need to increase the sample rate by a factor of 7x4 = 28.Eric, are you sure it's not 4^7 = 16384 ? Regards, Evgeny.

# BPSK one-bit

Started by ●July 24, 2015

Reply by ●July 25, 20152015-07-25

Reply by ●July 25, 20152015-07-25

On Sat, 25 Jul 2015 19:01:01 +0300, Evgeny Filatov <e.v.filatov@ieee.org> wrote:>On 25.07.2015 18:41, Eric Jacobsen wrote: > >(snip) > >> In general one can always trade sample rate for ADC precision, i.e., >> you can reduce the ADC precision by one bit if you increase the sample >> rate by a factor of four. So to reduce a eight-bit converter to >> one-bit, you need to increase the sample rate by a factor of 7x4 = 28. > >Eric, are you sure it's not 4^7 = 16384 ? > >Regards, >Evgeny.Derp! Yeah, brainfart on my part. So, yeah, it's ugly. It's especially ugly because now the initial stages of the decimating filters have to run at a very high clock rate. That's doable, but it does affect the tradeoff space. And there are other ways to get the necessary processing gain rather than getting it all from decimating filters, which may allow you to reduce the sample rate. This can be exploited in some radar systems, where there is often a lot of processing gain associated with compressing the return pulse. When I worked at Goodyear Aerospace (eons ago) they had built a SAR radar processor in the early 80s that had a 1-bit ADC, and got the processing gain from the two-dimensional algorithms used to create the SAR images. It worked pretty well. But there's a lot to understand and get right to make it all work. Eric Jacobsen Anchor Hill Communications http://www.anchorhill.com

Reply by ●July 25, 20152015-07-25

On Sat, 25 Jul 2015 18:30:51 +0000, Eric Jacobsen wrote:> On Sat, 25 Jul 2015 19:01:01 +0300, Evgeny Filatov > <e.v.filatov@ieee.org> wrote: > >>On 25.07.2015 18:41, Eric Jacobsen wrote: >> >>(snip) >> >>> In general one can always trade sample rate for ADC precision, i.e., >>> you can reduce the ADC precision by one bit if you increase the sample >>> rate by a factor of four. So to reduce a eight-bit converter to >>> one-bit, you need to increase the sample rate by a factor of 7x4 = 28. >> >>Eric, are you sure it's not 4^7 = 16384 ? >> >>Regards, >>Evgeny. > > Derp! Yeah, brainfart on my part. > > So, yeah, it's ugly. It's especially ugly because now the initial > stages of the decimating filters have to run at a very high clock rate. > That's doable, but it does affect the tradeoff space.However, those first stages just need to be counters, which helps. I think doing it in FPGA would end up easier than trying to do it with discretes, because you'll spend all your time hand-tuning the board layout, assuming you can find fast enough logic in the first place. -- www.wescottdesign.com

Reply by ●July 25, 20152015-07-25

On Sat, 25 Jul 2015 14:34:49 -0500, Tim Wescott <tim@seemywebsite.com> wrote:>On Sat, 25 Jul 2015 18:30:51 +0000, Eric Jacobsen wrote: > >> On Sat, 25 Jul 2015 19:01:01 +0300, Evgeny Filatov >> <e.v.filatov@ieee.org> wrote: >> >>>On 25.07.2015 18:41, Eric Jacobsen wrote: >>> >>>(snip) >>> >>>> In general one can always trade sample rate for ADC precision, i.e., >>>> you can reduce the ADC precision by one bit if you increase the sample >>>> rate by a factor of four. So to reduce a eight-bit converter to >>>> one-bit, you need to increase the sample rate by a factor of 7x4 = 28. >>> >>>Eric, are you sure it's not 4^7 = 16384 ? >>> >>>Regards, >>>Evgeny. >> >> Derp! Yeah, brainfart on my part. >> >> So, yeah, it's ugly. It's especially ugly because now the initial >> stages of the decimating filters have to run at a very high clock rate. >> That's doable, but it does affect the tradeoff space. > >However, those first stages just need to be counters, which helps. I >think doing it in FPGA would end up easier than trying to do it with >discretes, because you'll spend all your time hand-tuning the board >layout, assuming you can find fast enough logic in the first place.The main issue there is that you're forced into a speed grade that only a small fraction of the part may reall need, so the cost of the FPGA can be greatly affected.>-- >www.wescottdesign.comEric Jacobsen Anchor Hill Communications http://www.anchorhill.com

Reply by ●July 25, 20152015-07-25

On Sat, 25 Jul 2015 20:18:49 +0000, Eric Jacobsen wrote:> On Sat, 25 Jul 2015 14:34:49 -0500, Tim Wescott <tim@seemywebsite.com> > wrote: > >>On Sat, 25 Jul 2015 18:30:51 +0000, Eric Jacobsen wrote: >> >>> On Sat, 25 Jul 2015 19:01:01 +0300, Evgeny Filatov >>> <e.v.filatov@ieee.org> wrote: >>> >>>>On 25.07.2015 18:41, Eric Jacobsen wrote: >>>> >>>>(snip) >>>> >>>>> In general one can always trade sample rate for ADC precision, i.e., >>>>> you can reduce the ADC precision by one bit if you increase the >>>>> sample rate by a factor of four. So to reduce a eight-bit >>>>> converter to one-bit, you need to increase the sample rate by a >>>>> factor of 7x4 = 28. >>>> >>>>Eric, are you sure it's not 4^7 = 16384 ? >>>> >>>>Regards, >>>>Evgeny. >>> >>> Derp! Yeah, brainfart on my part. >>> >>> So, yeah, it's ugly. It's especially ugly because now the initial >>> stages of the decimating filters have to run at a very high clock >>> rate. >>> That's doable, but it does affect the tradeoff space. >> >>However, those first stages just need to be counters, which helps. I >>think doing it in FPGA would end up easier than trying to do it with >>discretes, because you'll spend all your time hand-tuning the board >>layout, assuming you can find fast enough logic in the first place. > > The main issue there is that you're forced into a speed grade that only > a small fraction of the part may reall need, so the cost of the FPGA can > be greatly affected.Hmm. True. OTOH, it may be possible to do just the initial decimation part in something little and lightning-fast, and then feed it to a slower FPGA or even (depending on the data rate and hence the required rate of the decimated output) a processor. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com

Reply by ●July 25, 20152015-07-25

On Fri, 24 Jul 2015 23:16:11 -0700, claudio.muzzini wrote:> Il giorno sabato 25 luglio 2015 05:45:57 UTC+8, Tim Wescott ha scritto: >> On Fri, 24 Jul 2015 14:20:11 -0700, claudio.muzzini wrote: >> >> > Il giorno sabato 25 luglio 2015 04:54:02 UTC+8, Eric Jacobsen ha >> > scritto: >> >> On Fri, 24 Jul 2015 13:22:46 -0700 (PDT), >> >> claudio.muzzini@muzzini.org wrote: >> >> >> >> >Il giorno sabato 25 luglio 2015 02:54:17 UTC+8, Tim Wescott ha >> >> >scritto: >> >> >> On Thu, 23 Jul 2015 22:37:44 -0700, claudio.muzzini wrote: >> >> >> >> >> >> > Dear group, >> >> >> > I would like to implement a BPSK demodulator with one-bit >> >> >> > signal processing. >> >> >> > I will use an Hard limiting IF and 1-bit A/D converter. >> >> >> > It is for coherent RADAR, so I have the clk. >> >> >> > I can sampling at maximum for time BW. >> >> >> > >> >> >> > Any idea? >> >> >> > >> >> >> > Thank you. >> >> >> > Best regards. >> >> >> > >> >> >> > -- >> >> >> >> >> >> What is your question? Do you have a specific issue you need >> >> >> help with, >> >> >> or do you want us to design your system for you? >> >> >> >> >> >> -- >> >> >> >> >> >> Tim Wescott Wescott Design Services http://www.wescottdesign.com >> >> > >> >> >I need the idea how to implement, let me say - block diagram - >> >> >principle schematic- >> >> >> >> The first block is the AFE, the Analog Front End, the next block is >> >> the ADC, the next block is the digital processing. >> >> >> >> Does that help? >> >> >> >> If not, you need to give more info. >> >> >> >> >-- >> >> >-- >> >> > >> >> > >> >> >*Claudio Muzzini*Mob. +39 3484321716 >> >> > >> >> >*Perfekt ist nicht genug.* >> >> >> >> Eric Jacobsen Anchor Hill Communications http://www.anchorhill.c >> > What about the Digital processing at "1-bit". >> > If you know hot implement, please post the block diagram AND/OR the >> > schematich. >> >> This is sounding ever more like you want us to do your work for you. >> For the most part people on this group are willing to answer questions >> that take between on word and five paragraphs, and that don't require >> much effort beyond the writing to answer. So "is this block diagram >> sound" (with a link) is a good question, but "gimme a block diagram" is >> not, unless it's a block diagram for something bog-standard. >> >> This may sound harsh, but we're unpaid here. We are willing to help, >> if you can present us with suitable questions. >> >> Signal processing chains with "1-bit" ADCs look pretty much the same at >> the block diagram level as signal processing chains with wider ADCs >> (for that matter, it can look a lot like a signal processing chain with >> no ADC at all). >> >> The only real difference is that when you have a 1-bit ADC is that you >> need to (a) sample way fast, and (b) make sure that there's enough >> noise or other out-of-band signal. Basically, you need an ADC output >> that has enough signal buried in the noise so that when you average the >> snot out of it there's useful signal. >> >> I do not, personally, know of a good source for you. It sounds like >> you're doing something moderately unique -- I would suggest that you >> look for tutorials or white papers on other devices that use 1-bit ADCs >> (consumer-grade GPS receivers and possibly even cell phones that use >> spread spectrum would be good starting places), then see if you can't >> extrapolate from the 1-bit wisdom there to your problem. >> >> -- >> >> Tim Wescott Wescott Design Services http://www.wescottdesign.com > > Hello Tim, > really thank you for your reply. > If i need to design this demodulator with "standard" A/D for example > 8bit, I do not have problem...I am a little bit confused about how to > implement the filter after the multiplier(mixer) when I use only one > bit. I do not want use FPGA but I would like to implement the > demodulator with TTL logic Thank youI assume you mean some CMOS variant with 74<whis-bang>Cxxx part numbers. I'm not sure why you want to have a huge inflexible board with lots of revisions when a single FPGA would do the job, but you can decimate the 1- bit ADC output by simple counting, then read that count at a lower rate and do your processing on that. If you need a mixer ahead of the filtering then implement it using an XOR gate before the decimation. (Work out the math: A XOR B looks like multiplication if you let x = true represent -1 and x = false represent +1.) -- Tim Wescott Wescott Design Services http://www.wescottdesign.com

Reply by ●July 25, 20152015-07-25

Il giorno sabato 25 luglio 2015 23:57:29 UTC+8, Evgeny Filatov ha scritto:> On 25.07.2015 9:16, claudio.muzzini@muzzini.org wrote: > > Il giorno sabato 25 luglio 2015 05:45:57 UTC+8, Tim Wescott ha scritto: > >> On Fri, 24 Jul 2015 14:20:11 -0700, claudio.muzzini wrote: > >> > >>> Il giorno sabato 25 luglio 2015 04:54:02 UTC+8, Eric Jacobsen ha > >>> scritto: > >>>> On Fri, 24 Jul 2015 13:22:46 -0700 (PDT), claudio.muzzini@muzzini.org > >>>> wrote: > >>>> > >>>>> Il giorno sabato 25 luglio 2015 02:54:17 UTC+8, Tim Wescott ha > >>>>> scritto: > >>>>>> On Thu, 23 Jul 2015 22:37:44 -0700, claudio.muzzini wrote: > >>>>>> > >>>>>>> Dear group, > >>>>>>> I would like to implement a BPSK demodulator with one-bit signal > >>>>>>> processing. > >>>>>>> I will use an Hard limiting IF and 1-bit A/D converter. > >>>>>>> It is for coherent RADAR, so I have the clk. > >>>>>>> I can sampling at maximum for time BW. > >>>>>>> > >>>>>>> Any idea? > >>>>>>> > >>>>>>> Thank you. > >>>>>>> Best regards. > >>>>>>> > >>>>>>> -- > >>>>>> > >>>>>> What is your question? Do you have a specific issue you need help > >>>>>> with, > >>>>>> or do you want us to design your system for you? > >>>>>> > >>>>>> -- > >>>>>> > >>>>>> Tim Wescott Wescott Design Services http://www.wescottdesign.com > >>>>> > >>>>> I need the idea how to implement, let me say - block diagram - > >>>>> principle schematic- > >>>> > >>>> The first block is the AFE, the Analog Front End, the next block is the > >>>> ADC, the next block is the digital processing. > >>>> > >>>> Does that help? > >>>> > >>>> If not, you need to give more info. > >>>> > >>>>> -- > >>>>> -- > >>>>> > >>>>> > >>>>> *Claudio Muzzini*Mob. +39 3484321716 > >>>>> > >>>>> *Perfekt ist nicht genug.* > >>>> > >>>> Eric Jacobsen Anchor Hill Communications http://www.anchorhill.c > >>> What about the Digital processing at "1-bit". > >>> If you know hot implement, please post the block diagram AND/OR the > >>> schematich. > >> > >> This is sounding ever more like you want us to do your work for you. For > >> the most part people on this group are willing to answer questions that > >> take between on word and five paragraphs, and that don't require much > >> effort beyond the writing to answer. So "is this block diagram > >> sound" (with a link) is a good question, but "gimme a block diagram" is > >> not, unless it's a block diagram for something bog-standard. > >> > >> This may sound harsh, but we're unpaid here. We are willing to help, if > >> you can present us with suitable questions. > >> > >> Signal processing chains with "1-bit" ADCs look pretty much the same at > >> the block diagram level as signal processing chains with wider ADCs (for > >> that matter, it can look a lot like a signal processing chain with no ADC > >> at all). > >> > >> The only real difference is that when you have a 1-bit ADC is that you > >> need to (a) sample way fast, and (b) make sure that there's enough noise > >> or other out-of-band signal. Basically, you need an ADC output that has > >> enough signal buried in the noise so that when you average the snot out > >> of it there's useful signal. > >> > >> I do not, personally, know of a good source for you. It sounds like > >> you're doing something moderately unique -- I would suggest that you look > >> for tutorials or white papers on other devices that use 1-bit ADCs > >> (consumer-grade GPS receivers and possibly even cell phones that use > >> spread spectrum would be good starting places), then see if you can't > >> extrapolate from the 1-bit wisdom there to your problem. > >> > >> -- > >> > >> Tim Wescott > >> Wescott Design Services > >> http://www.wescottdesign.com > > > > Hello Tim, > > really thank you for your reply. > > If i need to design this demodulator with "standard" A/D for example 8bit, I do not have problem...I am a little bit confused about how to implement the filter after the multiplier(mixer) when I use only one bit. I do not want use FPGA but I would like to implement the demodulator with TTL logic > > Thank you > > > > I thought the entire point of FPGAs was to simplify digital design. > > But if you are planning to use discreet components anyway, what is the > reason to make it digital? There are a lot of schematics for analog > demodulators. You can look up any older book, e.g. 1973 > "Telecommunication Systems Engineering" by Lindsey and Simon, which can > be used to build an analog BPSK demodulator. > > Regards, > Evgeny.Just for hobby! I can not find in internet an explanation how to implement a BPSK demodulator with TTL using 1-bit A/D. This is a reason of my request. Regards Claudio -- -- *Claudio Muzzini*Mob. +39 3484321716 *Perfekt ist nicht genug.*